RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Lavin, Christopher; Padilla, Marc; Lamprecht, Jaren; Lundrigan, Philip; Nelson, Brent; Hutchings, Brad

doi:10.1109/fpl.2011.69

Cited by 95 publications

(45 citation statements)

References 15 publications

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“…Unfortunately, the BLE usage cannot be directly obtained by counting the FFs, LUTs, or slices reported by the tool, as a Virtex 6 may use more than one FF per BLE, a LUT may be unused, and many slices may not be fully used but can be used for other logic. Therefore, the resulting netlist after place&route was converted to an XDL file, and the XDL-Parser from the RapidSmith Project [48] was used to obtain the BLEs directly from the netlist. All synthesis results are listed in Table 4.…”

Section: Resultsmentioning

confidence: 99%

FIR filter optimization for video processing on FPGAs

Kumm

Fanghänel

Möller

et al. 2013

EURASIP J. Adv. Signal Process.

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Two-dimensional finite impulse response (FIR) filters are an important component in many image and video processing systems. The processing of complex video applications in real time requires high computational power, which can be provided using field programmable gate arrays (FPGAs) due to their inherent parallelism. The most resource-intensive components in computing FIR filters are the multiplications of the folding operation. This work proposes two optimization techniques for high-speed implementations of the required multiplications with the least possible number of FPGA components. Both methods use integer linear programming formulations which can be optimally solved by standard solvers. In the first method, a formulation for the pipelined multiple constant multiplication problem is presented. In the second method, also multiplication structures based on look-up tables are taken into account. Due to the low coefficient word size in video processing filters of typically 8 to 12 bits, an optimal solution is found for most of the filters in the benchmark used. A complexity reduction of 8.5% for a Xilinx Virtex 6 FPGA could be achieved compared to state-of-the-art heuristics.

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Section: Resultsmentioning

confidence: 99%

FIR filter optimization for video processing on FPGAs

Kumm

Fanghänel

Möller

et al. 2013

EURASIP J. Adv. Signal Process.

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“…Therefore, a human-readable equivalent version of the NCD is created which allows design modifications exploiting an open source java based set of RapidSmith [22], [23]. We modified the RapidSmith based router published in [24] and such created our own rerouter which contains all nets of the design within the predetermined area on chip.…”

Section: B Implementation Methodologymentioning

confidence: 99%

Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures

Veljković

Riesgo

Torre

2015

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Abstract-The impact of SRAM-based FPGAs is constantly growing in aerospace industry despite the fact that their volatile configuration memory is highly susceptible to radiation effects. Therefore, strong fault-handling mechanisms have to be developed in order to protect the design and make it capable of fighting against both soft and permanent errors. In this paper, a fully reconfigurable medium-grained triple modular redundancy (TMR) architecture which forms part of a runtime adaptive onboard processor (OBP) is presented. Fault mitigation is extended to the voting mechanism by applying our reconfiguration methodology not only to domain replicas but also to the voter itself. The proposed approach takes advantage of adaptive configuration placement and modular property of the OBP, thus allowing on-line creation of different medium-grained TMRs and selection of their granularity level. Consequently, we are able to narrow down the fault-affected area thus making the error recovery process faster and less power consuming. The conventional hardware based voting is supported by the ICAPbased one in order to additionally strengthen the reconfigurable intermediate voting. In addition, the implementation methodology ensures using only one memory footprint for all voters and their voting adaptations thus saving storing resources in expensive rad-hard memories.

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“…For engineers and scientists who are interested in building their own netlist analysis and CAD tools, researchers from Brigham Young University present an interesting JAVA toolkit called RapidSmith [Lavin et al 2011]. The toolkit offers a rich Application Programming Interface (API) to parse, analyse and manipulate XDL files (which can be easily created from Xilinx netlists).…”

Section: Mitigation Design Techniques Aimed At Design-time Fault Avoimentioning

confidence: 99%

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

Siegle

Vladimirova

Ilstad³

et al. 2015

ACM Comput. Surv.

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The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.

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RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs

Cited by 95 publications

References 15 publications

FIR filter optimization for video processing on FPGAs

FIR filter optimization for video processing on FPGAs

Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures

Mitigation of Radiation Effects in SRAM-Based FPGAs for Space Applications

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