FIR filter optimization for video processing on FPGAs

Abstract

Two-dimensional finite impulse response (FIR) filters are an important component in many image and video processing systems. The processing of complex video applications in real time requires high computational power, which can be provided using field programmable gate arrays (FPGAs) due to their inherent parallelism. The most resource-intensive components in computing FIR filters are the multiplications of the folding operation. This work proposes two optimization techniques for high-speed implementations of the required multiplications with the least possible number of FPGA components. Both methods use integer linear programming formulations which can be optimally solved by standard solvers. In the first method, a formulation for the pipelined multiple constant multiplication problem is presented. In the second method, also multiplication structures based on look-up tables are taken into account. Due to the low coefficient word size in video processing filters of typically 8 to 12 bits, an optimal solution is found for most of the filters in the benchmark used. A complexity reduction of 8.5% for a Xilinx Virtex 6 FPGA could be achieved compared to state-of-the-art heuristics.

Table-Based versus Shift-And-Add Constant Multipliers for FPGAs

“…This can be understood considering the large LUTs of modern FPGAs. However, it was not expected, as previous work showed that the shift-and-add approach was better for input word sizes larger than 8 bit in the case of multiple constant multiplication [15]. This can be explained by the fact that in this case, much more sharing is possible when multiplying with several constants.…”

“…The two methods are reviewed in detail in Section II, the first objective of this work being too explicit which technique works best in which context. We are aware of only two earlier comparisons of KCM and shift-andadd [14], [15], both limited to the case of multiple constant multiplication (MCM) of small integer constants.…”

Efficient structural adder pipelining in transposed form FIR filters

“…The effect of pipelining MCM blocks was studied in [8]. Heuristic and exact minimization methods to directly pipeline the MCM block were proposed [9], [10].…”

Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

“…However, this type of operations has become very important mainly when the pipelined constant multiplication blocks are implemented in the increasingly demanded field programmable gate array (FPGA) platforms. This is due to the fact that logic blocks of FPGAs include memory elements, and thus, pipelining results in low extra cost [5][6][7][8][9][10][11][12]. Currently, the use of three-input adders has started to gain importance, since the logic blocks of the newest families of FPGAs are bigger and allow to fit more complex adders using nearly the same amount of hardware resources [10][11][12].…”

“…Nevertheless, the critical path has the main negative impact in the speed and power consumption [13][14][15][16][17][18]. Therefore, substantial research activity has been carried out currently targeting both, application-specific integrated circuits (ASICs) [19][20][21] and FPGAs [5][6][7][8][9][10][22][23][24][25], where the minimization of the number of arithmetic operations subject to a minimum number of depth levels is the ultimate goal.…”