We considu a general partitioning problem, namely. how to parution the elements of a circuit into sets of size less than a d l c~naant. SO that the number of nets whish connezt ekments in different s c l~ is minimized One application is in the design for lcstabillty of VLSl chip pod prinltd circuii boards [7, 8). We considex two different versions of a bouom-up i&ve improvement appoach. In & hrst version we pnscnt an ef6ciet-u htunstic.In an altemadveversion, we me the heuristic asasubrocline toan -ximation @ r~~a b i y g h ) algorithm, to d t in a m~i y good sdutions.We compare both approaches with the familiar topdown appmach which uses a well known bisection heurislic [ 5 ] as a subrwrine. Our solutions outperform Ihe ropdown partitioning approach.