Circuit partitioning into small sets: a tool to support testing with further applications

Abstract

We considu a general partitioning problem, namely. how to parution the elements of a circuit into sets of size less than a d l c~naant. SO that the number of nets whish connezt ekments in different s c l~ is minimized One application is in the design for lcstabillty of VLSl chip pod prinltd circuii boards [7, 8). We considex two different versions of a bouom-up i&ve improvement appoach. In & hrst version we pnscnt an ef6ciet-u htunstic.In an altemadveversion, we me the heuristic asasubrocline toan -ximation @ r~~a b i y g h ) algorithm, to d t in a m~i y good sdutions.We compare both approaches with the familiar topdown appmach which uses a well known bisection heurislic [ 5 ] as a subrwrine. Our solutions outperform Ihe ropdown partitioning approach.

On partitioning of hypergraphs

“…The EIP also finds applications in rapid prototyping where the goal typically is to partition a circuit into a minimal number of FPGAs (Field Programmable Gate Arrays) under different constraints such as available number of pins and routing resources [10,[14][15][16]23]. Another application area is the design for testability of VLSI circuits where the circuit is partitioned into smaller parts to facilitate testing [22]. However, the importance of the hypergraph partitioning problem goes beyond the VLSI design.…”