Rapid isothermal processing of strained GeSi layers

Nayak, Deepak Kumar; Kamjoo, K.; Park, J.S.; Woo, J.C.S.; Wang, K.L.

doi:10.1109/16.108212

Cited by 73 publications

(31 citation statements)

References 31 publications

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“…19,20 High process temperatures with short time periods are recommended to give a good oxide-semiconductor interface and conserve carrier confinement in SiGe. 7,18,27 Immediately after oxidation the wafers were put into the evaporation chamber for aluminum gate contact formation using a shadow mask method with a device diameter of 250 Ϯ10 m. Wet GaIn was applied on the backside for good ohmic contact.…”

Section: Methodsmentioning

confidence: 99%

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Effect of Si cap layer on parasitic channel operation in Si/SiGe metal–oxide–semiconductor structures

Sareen

Wang

Södervall

et al. 2003

Journal of Applied Physics

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Articles you may be interested inStrain response of high mobility germanium n-channel metal-oxide-semiconductor field-effect transistors on (001) substrates Appl. Phys. Lett. 99, 022106 (2011); 10.1063/1.3604417 Molecular-beam epitaxy growth of device-compatible GaAs on silicon substrates with thin ( 80 nm ) Si 1 − x Ge x step-graded buffer layers for high-κ III-V metal-oxide-semiconductor field effect transistor applications Study of strain relaxation in Si/SiGe metal-oxide-semiconductor field-effect transistors

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Section: Methodsmentioning

confidence: 99%

“…17 Wet oxidation results in accelerated nonlinear growth for SiGe. 6,7,18 From the literature 9-12 it is known that retention of a small cap layer is necessary for ultrashort channel devices. The Si cap is a critical component of Si/SiGe based MOS-FET devices.…”

Section: Introductionmentioning

confidence: 99%

Effect of Si cap layer on parasitic channel operation in Si/SiGe metal–oxide–semiconductor structures

Sareen

Wang

Södervall

et al. 2003

Journal of Applied Physics

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“…Considering the work functions for Al (4.16 eV), NiGe (5.2 eV), Ge (4.33 eV), and SiGe (4.55 eV) and the gate oxide thickness of 3-4 nm, our experimental observations of negative Vfb suggest estimated positive fixed charge densities of ~5 × 10 11 cm −2 at interfaces of SiO2/SiGe and SiO2/Ge dot. It is interesting to note that the positive fixed charges measured for our NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors are in contrast to the conventional expectation of negative fixed charges produced by the thermal oxidation of SiGe alloys (LeGoues et al, 1989;Nayak et al, 1990Nayak et al, , 1992 or at high-k dielectric/Ge interfaces generated either by chemical vapor deposition or atomic layer deposition (Bai et al, 2005;Zhang et al, 2006;Deng et al, 2011) As described in our previous reports (Kuo et al, 2012;Lai et al, 2015), the interfacial SiO2 layer between the Ge dot and the SiGe shell is formed by the thermal oxidation of Si interstitials that are released from the Si substrate. The oxide layer between the Ge dot and the deposited Al gate is formed by the thermal oxidation of Si interstitials that migrate along the surface of Ge dot to its distal end.…”

Section: Discussionmentioning

confidence: 64%

Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

et al. 2016

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We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/ SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe-nanopatterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5-90 nm), the SiO2 thickness (3-4 nm), and the SiGeshell thickness (2-15 nm) have been demonstrated, enabling a practically achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive X-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5 × 10 11 cm −2 eV −1 and fixed charge densities of 1-5 × 10 11 cm −2, suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1−xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.

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“…The generation of misfit dislocations as a result of substrate relaxation is not expected to occur at the temperatures used in this study. 41 Moreover, if the thermally induced relaxation of the strained Si 0.8 Ge 0.2 substrate was the cause for the degradation in electrical properties, one would expect to observe this behavior even in the case of hafnium-silicate films annealed in N 2 at 450°C. The C-V and J-V results for Pt/HfSiO/Si 0.8 Ge 0.2 (100) annealed at 450°C in N 2 (Fig.…”

Section: Resultsmentioning

confidence: 97%

The electrical properties and stability of the hafnium silicate/Si0.8Ge0.2(100) interface

Addepalli

Sivasubramani

Kim

et al. 2004

Journal of Elec Materi

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The effect of post-oxidation N 2 annealing and post-metallization forming-gas annealing on the electrical properties of Pt/Hf-silicate (3 nm)/Si 0.8 Ge 0.2 (100)/ n-type Si(100) metal-oxide semiconductor (MOS) capacitors is reported. Capacitance-voltage (C-V) and current density-voltage (J-V) measurements of asgrown, 3-nm-thick, hafnium-silicate films containing ϳ12at.%Hf indicate a large number of bulk and interface traps with a current density of ϳ10 Ϫ2 A/cm 2 at V FB ϩ 1 V. Post-ultraviolet (UV)/O 3 oxidation annealing in N 2 at 350°C for 30 min leads to a significant improvement in the electrical characteristics of the film. A post-metallization anneal (PMA) at 450°C for 30 min in forming gas (90% N 2 :10% H 2 ), however, degraded the electrical properties of the films. X-ray photoelectron spectroscopy (XPS) analyses of the forming-gas-annealed films indicate that a possible cause for the degradation in electrical properties is the hydrogen-induced reduction of GeO 2 in the interfacial Si x Ge 1-x O 2 oxide layer to elemental germanium. Implications for the introduction of hafnium silicate as a viable gate dielectric for SiGe-based devices are discussed.

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Rapid isothermal processing of strained GeSi layers

Cited by 73 publications

References 31 publications

Effect of Si cap layer on parasitic channel operation in Si/SiGe metal–oxide–semiconductor structures

Effect of Si cap layer on parasitic channel operation in Si/SiGe metal–oxide–semiconductor structures

Gate-Stack Engineering for Self-Organized Ge-dot/SiO2/SiGe-Shell MOS Capacitors

The electrical properties and stability of the hafnium silicate/Si0.8Ge0.2(100) interface

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