Effect of Si cap layer on parasitic channel operation in Si/SiGe metal–oxide–semiconductor structures

Abstract

Articles you may be interested inStrain response of high mobility germanium n-channel metal-oxide-semiconductor field-effect transistors on (001) substrates Appl. Phys. Lett. 99, 022106 (2011); 10.1063/1.3604417 Molecular-beam epitaxy growth of device-compatible GaAs on silicon substrates with thin ( 80 nm ) Si 1 − x Ge x step-graded buffer layers for high-κ III-V metal-oxide-semiconductor field effect transistor applications Study of strain relaxation in Si/SiGe metal-oxide-semiconductor field-effect transistors

Design and optimization of a buried channel PMOS integrable in a Si1−xGex BiCMOS process

“…A cap thickness down to 6-8 nm gives low values of D it [30], and thus is a good compromise between hole confinement and mobility. In one study, a 2.3 nm thick cap layer was found give minimal parasitic conduction in the Si cap layer [32]. They used an exact Si etch methodology and rapid thermal oxidation to achieve this.…”

Doping profile extraction in thin SOI films: Application to A2RAM

“…WITH TCAD To extract the bridge doping profile, we revisit the method described in [6][7][8][9][10][11]. The depletion depth depends on the gate voltage: a small signal variation on the metal modifies the depletion depth and the charge density at bottom of the film.…”

The electrical properties and stability of the hafnium silicate/Si0.8Ge0.2(100) interface

“…8 While the Si buffer layer affords a gate oxide (SiO 2 ) with outstanding electrical properties as well as a stable, high-quality Si/SiO 2 interface, it can also result in a parasitic, decreased mobility conduction channel, limiting the ultimate mobility that could be achieved with strained Si x Ge 1-x (100). 8,9 In addition, because of direct tunneling and concerns regarding dielectric reliability and breakdown strength as well as resistance to dopant penetration, ultrathin SiO 2 must be replaced by a physically thicker gate oxide material with a higher dielectric constant. 10 Therefore, in order to fully exploit the high carrier mobility in the case of high-performance SiGe-based devices, it is desirable to deposit a stable high-κ dielectric material in direct contact with Si x Ge 1-x (100).…”