Rapid hardware prototyping on RPM-2

Abstract

TODAY, THERE ARE MANY competingideas about how to implement multiprocessor systems. Although some of these ideas have been prototyped in hardware, hardware prototypes take too long to build and are very expensive. Often, by the time a hardware prototype really works, it is obsolete. First, the prototype's absolute speed is no longer on a par with current hardware. Second, the technology trade-offs among components change, so that performance results obtained on the prototype become meaningless. Third, the new architecture ideas embodied in the prototype may become irrelevant. Moreover, hardware prototypes are often hard to observe. By contrast, software simulations are very flexible, observable, and relatively inexpensive to develop. However, software simulations often force a trade-off between speed and realism.Hardware emulation using FPGAs (fieldprogrammable gate arrays) 1 is an intermediate approach between software simulation and hardware prototyping. We adopted this approach in a multiprocessor emulator called RPM (Rapid Prototyping Engine for Multiprocessor Systems). Because of its flexibility, the RPM hardware can adapt during its lifetime to the rapid evolution of technology trade-offs and new architectural ideas. RPM is also much more observable than typical hardware prototypes. RPM-2, the second RPM implementation, is up and running. Our first RPM-2 prototype is a cachecoherent nonuniform memory-access (CC-NUMA) multiprocessor. 2

Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution

“…Although, no real information about physical constraints of implementation are provided and till now there is no tested and approved tool assuming conversion of a TLM specification to a synthesizable RTL description. The idea of using FPGA platform for emulating parallel multiprocessors on chip have been used in the RPM [12] and RPM-2 [15] project. Although the approach is based on FPGA neither an automatic exploration flow nor a multi-objective design space exploration approach is proposed.…”

Experiments with the Fresh Breeze tree-based memory model

“…Tools for conducting system evaluation through simulation and emulation is an area of active work [25,26]. The RAMP project [27] at Berkeley is a FPGA-based many core emulation platform.…”