Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments

Jain, Abhishek Kumar; Lloyd, Scott; Gokhale, Maya

doi:10.1109/fccm.2018.00035

Cited by 13 publications

(6 citation statements)

References 13 publications

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“…One option would be to use a simulator (which is how Bornholt et al [2016] validated their crash-consistency models for filesystems) but this would not necessary reveal all the concurrency behaviours that real processors can exhibit. Another option, applicable when the processor-under-test is a component of a system-on-chip (SoC) FPGA [Jain et al 2018], is to build custom hardware to monitor the traffic to persistent memory, and thus to detect nvo violations without the need for crashes.…”

Section: Discussionmentioning

confidence: 99%

Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models

Raad

Wickerson

Vafeiadis

2019

Proc. ACM Program. Lang.

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Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance of volatile memory (RAM). To describe the persistency guarantees of NVM, several memory persistency models have been proposed in the literature. However, the formal persistency semantics of mainstream hardware is unexplored to date. To close this gap, we present a formal declarative framework for describing concurrency models in the NVM context, and then develop the PARMv8 persistency model as an instance of our framework, formalising the persistency semantics of the ARMv8 architecture for the first time. To facilitate correct persistent programming, we study transactions as a simple abstraction for concurrency and persistency control. We thus develop the PSER (persistent serialisability) persistency model, formalising transactional semantics in the NVM context for the first time, and demonstrate that PSER correctly compiles to PARMv8. This then enables programmers to write correct, concurrent and persistent programs, without having to understand the low-level architecture-specific persistency semantics of the underlying hardware. CCS Concepts: • Theory of computation → Concurrency; Semantics and reasoning; • Software and its engineering → General programming languages.

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Section: Discussionmentioning

confidence: 99%

Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models

Raad

Wickerson

Vafeiadis

2019

Proc. ACM Program. Lang.

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“…Our evaluations run application benchmarks under LiME. The LiME emulation framework 3 as shown in Figure 1 includes both hardware modules and software runtime libraries for the Zynq UltraScaleþ device on a ZCU102 development board. This MPSoC contains a fixed logic processing system (PS) region and a programmable logic (PL) region.…”

Section: Evaluation Methodologymentioning

confidence: 99%

“…2 In this paper, we focus on the memory latency spectrum to study application performance when main memory latency is varied by a factor of nearly 18-fold, from 45 to 800 ns. Using a multiprocessor system on chip (MPSoC) combining a multicore CPU with FPGA logic in the logic in memory emulator (LiME) 3 framework, we have emulated the performance of compute servers running data intensive benchmarks and mini-applications. We have conducted parameter sweeps in which the main memory latencies model the entire range from fast DRAM to SCM.…”

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confidence: 99%

Performance Assessment of Emerging Memories Through FPGA Emulation

2019

Self Cite

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Emerging memory technologies offer the prospect of large capacity, high bandwidth, and a range of access latencies ranging from DRAM-like to SSD-like. In this paper, we evaluate the performance of parallel applications on CPUs whose main memories sweep a wide range of latencies within a bandwidth cap. We use an FPGA emulator, the logic in memory emulator (LiME) to accelerate evaluation. The LiME framework uses a multiprocessor system on chip (MPSoC) combining multicore CPU, integrated memory controller, and FPGA fabric, and enables emulation orders of magnitude faster than software simulation. Our paper highlights the performance impact of higher latency on concurrent applications and identifies conditions under which future high latency memories can effectively be used as main memory.

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“…To address this, as a third direction of future work we intend to build custom hardware that allows us to monitor the traffic to persistent memory, and thus to observe nvo directly. This can be achieved when the processor under test is a component of a system-on-chip (SoC) FPGA [Jain et al 2018]. We can then use our Alloy-generated litmus tests as a conformance suite to test for nvo violations.…”

Section: Related and Future Workmentioning

confidence: 99%

Persistency semantics of the Intel-x86 architecture

Raad

Wickerson

Neiger

et al. 2019

Proc. ACM Program. Lang.

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Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance of RAM. To describe the persistency guarantees of NVM, several memory persistency models have been proposed in the literature. However, the persistency semantics of the ubiquitous x86 architecture remains unexplored to date. To close this gap, we develop the Px86 ('persistent x86') model, formalising the persistency semantics of Intel-x86 for the first time. We formulate Px86 both operationally and declaratively, and prove that the two characterisations are equivalent. To demonstrate the application of Px86, we develop two persistent libraries over Px86: a persistent transactional library, and a persistent variant of the MichaelśScott queue. Finally, we encode our declarative Px86 model in Alloy and use it to generate persistency litmus tests automatically.

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Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments

Cited by 13 publications

References 13 publications

Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models

Weak persistency semantics from the ground up: formalising the persistency semantics of ARMv8 and transactional models

Performance Assessment of Emerging Memories Through FPGA Emulation

Persistency semantics of the Intel-x86 architecture

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