Performance Assessment of Emerging Memories Through FPGA Emulation

Abstract

Emerging memory technologies offer the prospect of large capacity, high bandwidth, and a range of access latencies ranging from DRAM-like to SSD-like. In this paper, we evaluate the performance of parallel applications on CPUs whose main memories sweep a wide range of latencies within a bandwidth cap. We use an FPGA emulator, the logic in memory emulator (LiME) to accelerate evaluation. The LiME framework uses a multiprocessor system on chip (MPSoC) combining multicore CPU, integrated memory controller, and FPGA fabric, and enables emulation orders of magnitude faster than software simulation. Our paper highlights the performance impact of higher latency on concurrent applications and identifies conditions under which future high latency memories can effectively be used as main memory.

A Novel Resistive Switching Identification Method through Relaxation Characteristics for Sneak-path-constrained Selectorless RRAM application

“…In recent years, memory technology includes static random access memory (SRAM), dynamic random access memory (DRAM), flash memory are encountering challenges due to the continued scaling down of the designs 1–4 . Among several types of next generation memory devices, resistive random access memory (RRAM) composed of a simple metal-insulator-metal (MIM) structure has increasingly been attracting much attention as a promising candidate for next-generation nonvolatile emerging memory according to its potentially ultra-high density production probability, faster switching speed (<10 ns), compatibility with a crossbar structure with CMOS integration, lower energy consumption, and the feasibility for neuromorphic computing architecture design 5–10 .…”

Implementation and Optimization of SpMV algorithm based on SW26010P many-core processor and stored in BCSR format

“…In order to adapt the underlying architecture of hardware accelerators, researchers focus on the reconstruction of SpMV algorithm to improve the computing performance of hardware accelerators. Such as Intel Xeon Phi 10,11 , general purpose Graphics Processor (GPGPU) 12,13 , advanced micro devices (AMD) 14,15 , field programmable gate array (FPGA) 16,17 and so on. With the advent of Sunway Taihulight supercomputer 18 , it is equipped with SW26010P many-core processor unique hardware architecture and has strong parallel computing capabilities.…”

Implementation and optimization of SpMV algorithm based on SW26010P many-core processor and stored in BCSR format

“…In order to adapt the underlying architecture of hardware accelerators, researchers focus on the reconstruction of SpMV algorithm to improve the computing performance of hardware accelerators. Such as Intel Xeon Phi 10 , 11 , general purpose Graphics Processor (GPGPU) 12 , 13 , advanced micro devices (AMD) 14 , 15 , field programmable gate array (FPGA) 16 , 17 and so on. With the advent of Sunway Taihulight supercomputer 18 , it is equipped with SW26010P many-core processor unique hardware architecture and has strong parallel computing capabilities.…”