RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder

Akbari, Omid; Kamal, Mehdi; Afzali-Kusha, Ali; Pedram, Massoud

doi:10.1109/tcsii.2016.2633307

Cited by 118 publications

(83 citation statements)

References 15 publications

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“…This is a popular method because of its simplicity, but the work risks being applicable only to the tested application. Examples of such works [23,24] have utilized approximate multipliers and adders in image processing scenarios. The error metric then is measured on the test data (input images) and how well the approximate circuits formed the image as opposed to the ideal situation.…”

Section: Related Workmentioning

confidence: 99%

Error metrics determination in functionally approximated circuits using SAT solvers

2020

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Approximate computing is an emerging design paradigm that offers trade-offs between output accuracy and computation efforts by exploiting some applications' intrinsic error resiliency. Computation of error metrics is of paramount importance in approximate circuits to measure the degree of approximation. Most of the existing techniques for evaluating error metrics apply simulations which may not be effective for evaluation of large complex designs because of an immense increase in simulation runtime and a decrease in accuracy. To address these deficiencies, we present a novel methodology that employs SAT (Boolean satisfiability) solvers for fast and accurate determination of error metrics specifically for the calculation of an average-case error and the maximum error rate in functionally approximated circuits. The proposed approach identifies the set of all errors producing assignments to gauge the quality of approximate circuits for real-life applications. Additionally, the proposed approach provides a test generation method to facilitate design choices, and acts as an important guide to debug the approximate circuits to discover and locate the errors. The effectiveness of the approach is demonstrated by evaluating the error metrics of several benchmark-approximated adders of different sizes. Experimental results on benchmark circuits show that the proposed SAT-based methodology accurately determines the maximum error rate and an average-case error within acceptable CPU execution time in one go, and further provides a log of error-generating input assignments. OPEN ACCESSCitation: Abed S, Behiry AAMR, Ahmad I (2020) Error metrics determination in functionally approximated circuits using SAT solvers. PLoS ONE 15(1): e0227745. https://doi.org/10.

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Section: Related Workmentioning

confidence: 99%

Error metrics determination in functionally approximated circuits using SAT solvers

2020

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“…In [1], via modifying the Karnaugh map of a pair of 2×2 number, AN approximate2×2 number with a less complicated structure has been projected. AN incorrect number fashion methodology supported redesigning the multiplier into a pair of multiplication and nonmultiplication elements became delivered The multiplication 1/2 changed into designed supported the traditional multipliers whereas the non-multiplication 0.5 became enforced in an inexactarchitecture with comprehensive of well value of mistakes.…”

Section: Literature Surveymentioning

confidence: 99%

“…AN incorrect number fashion methodology supported redesigning the multiplier into a pair of multiplication and nonmultiplication elements became delivered The multiplication 1/2 changed into designed supported the traditional multipliers whereas the non-multiplication 0.5 became enforced in an inexactarchitecture with comprehensive of well value of mistakes. It has to be compelled to be expressed that each of the ways given in [1] be afflicted by using immoderate relative mistakes. In [8], a static part methodology (SSM) is given, that performs the multiplication operation on an 'm' bit section ranging from little of the enter operands the place m is ample or larger than n/2.…”

Section: Literature Surveymentioning

confidence: 99%

Design and Implementation of Dual Mode Compressor Based32 Bitdadda Multiplier using Modified Carry Select Adder

Swapnika*,

Ganesh

2019

IJITEE

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In this paper, we tend to advocate 4:2 compressors, that have the flexibleness of trade between the particular andinexact operational modes.Multiplicationis based totally on multiply and adder unit,filtering,convolution which are extensively used in applications of signal processing. As, multiplication takes more execution time in DSP structures, there is need to develop high pace multipliers.In the approximate mode, those dual compressors offer quickness and decrease current consumptions on the fee of lower accuracy.Every single compressors has its personal diploma of efficiency interior the approximate mode moreover to one-of-a-kind delays and strength dissipations internal the approximate and true modesexploitation these compressors inside the buildings of parallel multipliers affords configurable multipliers whose accuracies (as properly as their powers and speeds) can even change dynamically at some stage within the runtime. The proficiency of this compressors in 32-bit Dadda multiplier factor are evaluated exploitation VerilogHDL and simulated and synthesized the usage of XILINX ISE style healthy evaluated by using the employment of modified Carry opt for adder.Comparing their parameters with those of the existing dadda multiplier designed using 4:2 compressors

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“…We review a few representative works on ACA design and show the relation with our method. These designs can be generally categorized into two groups: error-correction-based configurations [1]- [3] and carry-prediction-based configurations [4], [5]. The main idea of an error-correction-based approach [1]- [3] is shown in Fig.…”

Section: Literature Reviewmentioning

confidence: 99%

“…Since the error correction circuits are usually pipelined, an accurate computation may take multiple clock cycles and could stall the entire data path, depending on the addend values. The frame work of carry-prediction-based methods [4], [5] is shown in Fig. 2.…”

Section: Literature Reviewmentioning

confidence: 99%

Design and Analysis of an Energy-Efficient Accuracy Configurable Adder

Pathak¹

2019

IJRASET

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The approximate adders proposed in literature are dedicated for error-resilient applications only. These adders cannot be used in the domain where conventional adders are used or applications where we need to handle critical data with accuracy. So in this paper we proposed a Simple Accuracy Configurable Adder (SACA) that can be used in two different modes, Accurate Mode and Approximate Mode. The amount of error to be introduced at each stage is controlled with help of MUX. Further we evaluated the performance of Accuracy Configurable Adder in terms of delay, power, PDP, EDP and error characteristics. SACA is 28.36% faster and consumes 30.11% less power than RCA. PDP is the figure of merit for digital logic circuits. The less is the value of PDP, the more Energy-efficient is circuit. SACA provides 47% less PDP and 62% less EDP as compared to RCA.

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RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder

Cited by 118 publications

References 15 publications

Error metrics determination in functionally approximated circuits using SAT solvers

Error metrics determination in functionally approximated circuits using SAT solvers

Design and Implementation of Dual Mode Compressor Based32 Bitdadda Multiplier using Modified Carry Select Adder

Design and Analysis of an Energy-Efficient Accuracy Configurable Adder

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