Ranking Cryptographic Algorithms

Kieselmann, Olga; Kopal, Nils; Wacker, Arno

doi:10.1007/978-3-319-05044-7_9

Cited by 1 publication

(6 citation statements)

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“…Throughput has been measured from post‐route simulation of ISIM environment. The parameter security is measured with the help of [8]. The offline power, throughput, resource, and security data is stored in the three‐dimensional matrix and are added as a header file of the preferential algorithm executed by PE1.…”

Section: Implementation and Resultsmentioning

confidence: 99%

“…Formulation of new ESI: Here, we propose an automated preferential algorithm which introduces a new ESI to meet the multi-metric budget consisting of resource, power, and throughput and security on SSL cipher suite. The security parameter S is defined by [8]…”

Section: Security-aware Esi Incorporating Hardware Variancementioning

confidence: 99%

“…At the first clock cycle, the non-linear feedback shift storage block named as nfsr take key and linear feedback storage shift register takes the 64 bits IV and rest 16 bit initialised by '1's. Using (8) and (7), the two functions g(x) and f (x), respectively, are computed which are driven to the most significant bits of these two shift registers with a…”

Section: Crypto Variantsmentioning

confidence: 99%

“…If we compensate very little resource and power, grain can be accelerated by 16 times by loop unrolling factor. It is seen that shifting is done from MSB to LSB, and the used MSB in g(x), f (x), and h(x) used in (8), (7), and (7), respectively, is 63rd position. Hence, the maximum loop unrolling factor possible in grain is 16.…”

Section: Crypto Variantsmentioning

confidence: 99%

“…Even for recent SSL/TLS version, outdated DES and broken MD5 exist. Here, one can argue that those unsecure algorithms should not be offered in the recent framework, but this would not be a good solution, since unsecure algorithm may have their own merits [8]. Here, in our proposal, we incorporate a security parameter along with power, throughput, and resource which provides additional security information to the hardware developers.…”

Section: Introductionmentioning

confidence: 99%

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Hardware variant NSP with security‐aware automated preferential algorithm

Paul

Sikder

Chakrabarti

et al. 2018

IET Computers & Digital Techniques

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Efficient and cost-effective hardware design of network security processor (NSP) is of vital importance in the present era due to the increasing need of security infrastructure in a wide range of computing applications. Here, the authors propose an NSP in field programmable gate array (FPGA) platform where according to a strict power, throughput, resource, and security priorities, a proposed preferential algorithm chooses a cipher suite to program the hardware. The choice is based on a rank list of available cipher suites depending on efficient system index evaluated in terms of power, throughput, resource, and security data and their given weights by the user. Encryption, hash, and key exchange algorithm along with their architectural variants serve excellent hardware flexibility whose bit files are stored in secure digital memory. The proposed design used an isolated key memory where secret keys are stored in encrypted form along with the hash value. The design is implemented using ISE14.4 suite with ZYNQ7z020-clg484 FPGA platform. The performances of the variants architecture of the crypto algorithms are considerably better in terms of power, throughput, and resource than the existing works reported in the literature.

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Section: Implementation and Resultsmentioning

confidence: 99%

Section: Security-aware Esi Incorporating Hardware Variancementioning

confidence: 99%

Section: Crypto Variantsmentioning

confidence: 99%

Section: Crypto Variantsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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