Range-chart-guided iterative data-flow graph scheduling

Groot, S.M. Heemstra de; Gerez, Sabih H.; Herrmann, O.E.

doi:10.1109/81.139286

Cited by 74 publications

(31 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Already, the results match and even outperform that obtained in [11]. In addition, the ABFbased method has the benefit that it can handle any number of voltages/processors, and can also easily be extended to other problems, such as homogeneous processor scheduling [12]. Table 2 shows the power-savings that were obtained on the examples from [11].…”

Section: Search Techniques For Schedulingmentioning

confidence: 49%

Adaptive negative cycle detection in dynamic graphs

Chandrachoodan

Bhattacharyya

Liu

2001

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

View full text Add to dashboard Cite

We examine the problem of detecting negative cycles in a dynamic graph, which is a fundamental problem that arises in electronic design automation and systems theory.We introduce the concept of adaptive negative cycle detection, in which a graph changes over time, and negative cycle detection needs to be done periodically, but not necessarily after every individual change. Such scenarios arise, for example, during iterative design space exploration for hardware and software synthesis. We present an algorithm for this problem, called the Adaptive Bellman-Ford (ABF) algorithm, based on a novel extension of the well known Bellman-Ford algorithm. The ABF algorithm allows us to systematically adapt information for a given graph to a modified version of the graph. We show that the ABF algorithm significantly outperforms previously available approaches for dynamic graphs, which either recompute negative cycle information from scratch whenever a graph is modified, or process the modifications one at a time ("incrementally").As an application of the ABF technique, we show that it can be used to obtain a very fast implementation of Lawler's technique for the computation of the maximum-cycle mean (MCM) of a graph, especially for a certain important kind of sparse graph. We further illustrate the application of the ABF technique to design-space exploration by developing automated search techniques for scheduling iterative data-flow graphs.

show abstract

Section: Search Techniques For Schedulingmentioning

confidence: 49%

Adaptive negative cycle detection in dynamic graphs

Chandrachoodan

Bhattacharyya

Liu

2001

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

View full text Add to dashboard Cite

show abstract

“…Delay elements, however, are treated differently [1,2,3]. In sequential logic circuits, all delays are treated as flip-flops that are triggered on a common clock edge.…”

Section: Requirements Of a Timing Modelmentioning

confidence: 99%

“…, and § to refer to the sum V t $ p 3 $ t Figure 3: Second order filter section [3]. the data on the system.…”

Section: The Hierarchical Timing Pair Modelmentioning

confidence: 99%

“…These delay elements roughly correspond to registers in a hardware implementation, but are more flexible in that they do not impose the restriction that all the delay elements are activated at the same instant of time [1,2,3]. This allowance for variable phase clocking is an important way in which HLS differs from combinational logic implementation.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

The hierarchical timing pair model

Chandrachoodan

Bhattacharyya

Liu

2001

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)

View full text Add to dashboard Cite

We present a new model for representing timing information for functions in High-Level Synthesis (HLS). We identify shortcomings of the conventional timing model, which is a very simple model derived from the combinational logic model, and show that our new model overcomes many of these defects. In particular, we are able to provide a unified timing model that describes hierarchical combinational and iterative circuits and provides a compact representation of the information, that can be used to streamline system performance analysis.We present experimental results that demonstrate the effectiveness of our new approach, and describe an efficient algorithm to easily compute the required timing parameters from a description of the graph.

show abstract

“…chronization, and can be used as post-processing steps to any of the partitioning algorithms discussed in Section 4, as well as to a wide variety of multiprocessor scheduling algorithms for dataflow graphs, such as those described in [19,24,47].…”

Section: Synchronization Optimizationmentioning

confidence: 99%

Hardware/Software Cosynthesis of DSP Systems

Bhattacharyya¹

2001

Signal Processing and Communications

View full text Add to dashboard Cite

This chapter focuses on the automated mapping of high level specifications of DSP applications into implementation platforms that employ programmable DSPs. Since programmable DSPs are often used in conjunction with other types of programmable processors, such as microcontrollers and general-purpose microprocessors, and with various types of hardware modules, such as FPGAs, and ASIC circuitry, this mapping task, in general, is one of cosynthesis -the joint synthesis of both hardware and software -for a heterogeneous multiprocessor.Since a large variety of cosynthesis techniques have been developed to date, it is not possible here to provide comprehensive coverage of the field. Instead, we focus on a subset of topics that are central to DSP-oriented cosynthesis -application modeling, hardware/software partitioning, synchronization optimization, and block-processing. Some important topics related to cosynthesis that are not covered here include memory management [1,11,26,37,53], which is discussed in Chapter 10; DSP code generation from procedural language specifications [39], which is the topic of Chapter 7; and performance analysis [36,49,54].Additionally, we focus on synthesis from coarse-grain dataflow models due to the increasing importance of such modeling in DSP design tools, and the ability of such modeling to expose valuable, high-level structure of DSP applications that is difficult to deduce from within compilers for general purpose programming models, and other types of models. Thus, we do not explore techniques for fine-grain cosynthesis [21], including synthesis of applicationspecific instruction processors (ASIPs) [43], nor do we explore cosynthesis for control-dominant systems, such as those based on procedural language specifications [22], communicating sequential processes [50], and finite state machine models [6]. All of these are important directions within cosynthesis research, but they do not fit centrally within the DSP-oriented scope of this chapter.

show abstract

Range-chart-guided iterative data-flow graph scheduling

Cited by 74 publications

References 21 publications

Adaptive negative cycle detection in dynamic graphs

Adaptive negative cycle detection in dynamic graphs

The hierarchical timing pair model

Hardware/Software Cosynthesis of DSP Systems

Contact Info

Product

Resources

About