Random telegraph noise in highly scaled nMOSFETs

Abstract

Recently, 1/f and random telegraph noise (RTN) studies have been used to infer information about bulk dielectric defects' spatial and energetic distributions. These analyses rely on a noise framework which involves charge exchange between the inversion layer and the bulk dielectric defects via elastic tunneling. In this study, we extracted the characteristic capture and emission time constants from RTN in highly scaled nMOSFETs and showed that they are inconsistent with the elastic tunneling picture dictated by the physical thickness of the gate dielectric (1.4 nm). Consequently, our results suggest that an alternative model is required and that a large body of the recent RTN and 1/f noise defect profiling literature very likely needs to be re-interpreted.

A microscopic physical description of RTN current fluctuations in HfO<inf>x</inf> RRAM

“…The continuous aggressive scaling of Complementary Metal Oxide Semiconductor (CMOS) technology is enhancing phenomena related to charge trapping at defects created by the electrical stress, such as Stress-Induced Leakage Current (SILC) [1], Bias Temperature Instability (BTI) [2], and Random Telegraph Noise (RTN) [3]. Despite the intense research efforts dedicated to explore the role of defects in electronic devices [4][5][6], the physical mechanisms of BTI and RTN phenomena have been not unambiguously identified.…”

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…The original approach in [122] relied on the classical theory of direct tunneling into oxide defects [80,81], explicitly linking τ c and τ e to the space and energy position of the trap inside the oxide. Later results have, however, shown that capture/emission times in MOSFETs are not compatible with such a description [143,144], due to device variability effects on the time constants [145][146][147] and structural relaxation of defects [140,148], generating a large spread in time constants even for traps located close to the silicon/oxide interface and disrupting the classical correlation between τ c and τ e . The study of the microscopic properties of RTN traps is still an active research topic [149][150][151][152][153][154][155][156], but for our purposes we will adopt a pragmatic approach, assuming given distributions of capture/emission time constants that may be consistent with observations, without linking them to any particular trap location.…”

The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices

“…Frequency dispersion in accumulation or inversion region of capacitance-voltage (C-V) measurements is a typical characteristic of border trap interaction. But in such regions of a MOS C-V, the conventional MOS capacitor admittance model [18] is unsound. Moreover, the models developed in the past for border traps cannot explain the strong temperature and voltage dependence observed in admittance and reliability measurements [9,18,19].…”

“…But in such regions of a MOS C-V, the conventional MOS capacitor admittance model [18] is unsound. Moreover, the models developed in the past for border traps cannot explain the strong temperature and voltage dependence observed in admittance and reliability measurements [9,18,19]. We developed a detailed admittance model and a capacitor AC admittance based characterization methodology for border traps (traps within ~3 nm of the dielectric-semiconductor interface, see fig.…”