Random Active Shield

Briais, Sébastien; Cioranesco, Jean-Michel; Danger, Jean‐Luc; Guilley, Sylvain; Naccache, David; Porteboeuf, Thibault

doi:10.1109/fdtc.2012.11

Cited by 36 publications

(13 citation statements)

References 3 publications

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“…The silicon-surface protection layer is sometimes called the "top metal layer" because it is the top layer of several metal layers. in other cases, the top layer is called the "active shield" [5], "protection layer," "metal shield," or "top metal." In this paper, the title "silicon-surfaceprotection layer" is used because the term "active shield" is widely used in the areas of magnetic-field shielding and noise shielding.…”

Section: Physical-level-attack Detailsmentioning

confidence: 99%

“…10, it is evident that their shapes are non-typical; their patterns are not connected and each line is randomly shaped. This is called a "random active shield" [5], whereby it is more difficult for an FIB to cut and reconnect due to the nature of the protection; therefore, the protective-security level is very high, but, to implement a random active shield, at least two more metal layers are required, and this costs more than other silicon-surface-protection methods.…”

Section: Random Active Shield [5]mentioning

confidence: 99%

“…A random silicon-surface-protection layer [5] is very effective, but it requires at least two metal layers to implement. To calculate the routing overhead, the cost of one metal layer is equal to 5% of the chip size; because an additional metal layer is used, the silicon-chip size is reduced by approximately 5% to 10%.…”

Section: Performance Measurementmentioning

confidence: 99%

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Practical Silicon-Surface-Protection Method using Metal Layer

Yi¹,

Park²,

Kim³

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The reversal of a silicon chip to find out its security structure is common and possible at the present time. Thanks to reversing, it is possible to use a probing attack to obtain useful information such as personal information or a cryptographic key. For this reason, security-related blocks such as DES (Data Encryption Standard), AES (Advanced Encryption Standard), and RSA (Rivest Shamir Adleman) engines should be located in the lower layer of the chip to guard against a probing attack; in this regard, the addition of a silicon-surface-protection layer onto the chip surface is a crucial protective measure. But, for manufacturers, the implementation of an additional silicon layer is burdensome, because the addition of just one layer to a chip significantly increases the overall production cost; furthermore, the chip size is increased due to the bulk of the secure logic part and routing area of the silicon protection layer. To resolve this issue, this paper proposes a practical siliconsurface-protection method using a metal layer that increases the security level of the chip while minimizing its size and cost. The proposed method uses a shift register for the alternation and variation of the metal-layer data, and the inter-connection area is removed to minimize the size and cost of the chip in a more extensive manner than related methods.

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Section: Physical-level-attack Detailsmentioning

confidence: 99%

Section: Random Active Shield [5]mentioning

confidence: 99%

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Practical Silicon-Surface-Protection Method using Metal Layer

Yi¹,

Park²,

Kim³

2016

JSTS:Journal of Semiconductor Technology and Science

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“…multiple jogs). If the chip has a shield layer (refer to [10]), then the image recognition might be harder.…”

Section: B Medium Cost Hardware Trojan Horse Detectionmentioning

confidence: 99%

Hardware Trojan Horses in Cryptographic IP Cores

Bhasin

Danger

Guilley

et al. 2013

2013 Workshop on Fault Diagnosis and Tolerance in Cryptography

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106

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Abstract-Detecting hardware trojans is a difficult task in general. In this article we study hardware trojan horses insertion and detection in cryptographic intellectual property (IP) blocks. The context is that of a fabless design house that sells IP blocks as GDSII hard macros, and wants to check that final products have not been infected by trojans during the foundry stage. First, we show the efficiency of a medium cost hardware trojans detection method if the placement or the routing have been redone by the foundry. It consists in the comparison between optical microscopic pictures of the silicon product and the original view from a GDSII layout database reader. Second, we analyze the ability of an attacker to introduce a hardware trojan horse without changing neither the placement nor the routing of the cryptographic IP logic. On the example of an AES engine, we show that if the placement density is beyond 80%, the insertion is basically impossible. Therefore, this settles a simple design guidance to avoid trojan horses insertion in cryptographic IP blocks: have the design be compact enough, so that any functionally discreet trojan necessarily requires a complete re-place and re-route, which is detected by mere optical imaging (and not complete chip reverse-engineering).Index Terms-Hardware trojan horses (HTH), HTH detection and insertion, optical pictures versus GDSII comparison technique, ECO place-and-route, core utilization rate (CUR).

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“…In addition, tailored packaging cannot guarantee resistance against attacks from the reverse side of the chip. Another possibility is to install an active shield on or around the LSI to be protected [3][4][5]. However, the power needed to drive signals through the shield is non-trivial.…”

Section: Introductionmentioning

confidence: 99%

Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks

et al. 2015

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This paper presents a standard-cell-based semiautomatic design methodology for a new conceptual countermeasure against electromagnetic (EM) analysis and fault-injection attacks. The countermeasure, called the EM attack sensor, utilizes LC oscillators that react to variations in the EM field around a cryptographic LSI caused by a microprobe brought near the LSI. A dual-coil sensor architecture with digital calibration based on lookup table programming can prevent various microprobe-based EM attacks that cannot be thwarted by conventional countermeasures. All components of the sensor core are semiautomatically designed by standard electronic design automation tools with a fully digital standard cell library and hence minimum design cost. This sensor can therefore be scaled together with the cryptographic LSI to be protected. The sensor prototype is designed based on the proposed methodology together with a 128-bit-key composite AES processor in 0.18-µm CMOS with overheads of only 2 % in area, 9 % in power, and 0.2 % in performance, respectively. The countermeasure has been validated against a variety of EM attack scenarios. In particular, some further experimental results are shown for a detailed discussion.

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Random Active Shield

Cited by 36 publications

References 3 publications

Practical Silicon-Surface-Protection Method using Metal Layer

Practical Silicon-Surface-Protection Method using Metal Layer

Hardware Trojan Horses in Cryptographic IP Cores

Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks

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