Rail‐to‐rail complementary input StrongARM comparator for low‐power applications

Al-Qadasi, Mohammed; Alshehri, Abdullah; Alturki, Abdullah; Almansouri, Abdullah S.; Salama, Khaled N.; Fariborzi, Hossein; Al-Attar, Talal

doi:10.1049/iet-cds.2019.0361

Cited by 5 publications

(4 citation statements)

References 8 publications

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“…Therefore, to support data conversion across the entire dynamic range, the proposed FS ADC requires comparators that can perform rail-to-rail detection and high-speed operation. Figure 10a shows the comparator proposed in the literature [30]. It utilizes both NMOS and PMOS differential input pairs, enabling operation over the full dynamic range and achieving sufficient speed, rendering it suitable for the proposed architecture.…”

Section: High-speed Rail-to-rail Comparatormentioning

confidence: 99%

Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter

Lee,

Kim

2024

Electronics

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This study presents a charge-domain SRAM-based in-memory computing (IMC) architecture. The multiply-and-accumulate (MAC) operation in the IMC structure is divided into current- and charge-domain methods. Current-domain IMC has high-power consumption and poor linearity. Charge-domain IMC has reduced variability compared with current-domain IMCs, achieving higher linearity and enabling energy-efficient operation with fewer dynamic current paths. The proposed IMC structure uses a 9T1C bitcell considering the trade-off between the bitcell area and the threshold voltage drop by an NMOS access transistor. We propose an energy-efficient summation mechanism for 4-bit weight rows to perform energy-efficient MAC operations. The generated MAC value is finally returned as a digital value through an analog-to-digital converter (ADC), whose performance is one of the critical components in the overall system. The proposed flash-successive approximation register (SAR) ADC is designed by combining the advantages of flash ADC and SAR ADC and outputs digital values at approximately half the cycle of SAR ADC. The proposed charge-domain IMC is designed and simulated in a 65 nm CMOS process. It achieves 102.4 GOPS throughput and 33.6 TOPS/W energy efficiency at array size of 1 Kb.

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Section: High-speed Rail-to-rail Comparatormentioning

confidence: 99%

Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter

Lee,

Kim

2024

Electronics

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“…1. We used the comparator presented in [10] and shown in Fig. 4 to provide a comparison to the analog comparator.…”

Section: Possible Improvements Of Proposed Fcmentioning

confidence: 99%

“…4. Schematic of a dynamic clocked comparator presented in [10]. all circumstances, using a edge detector sensitive to only one edge type is highly recommended.…”

Section: Possible Improvements Of Proposed Fcmentioning

confidence: 99%

Low-Power CMOS Frequency Comparator

Kovac

Potocny

Arbet

et al. 2023

2023 46th MIPRO ICT and Electronics Convention (MIPRO)

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This paper is focused on the design and analysis of a fully on-chip frequency comparator (FC) implemented in 65 nm CMOS technology. The proposed FC employs a digital pre-processing stage followed by a rail-to-rail input and output (RRIO) voltage comparator, with low power consumption in units of µW. Evaluation accuracy is maintained for input frequencies up to 1 MHz. The FC is designed for the supply voltage of 1.2 V. The FC accepts signals with independent duty cycles and delays, without any correlation between the signals, making it an universal building block of more complex integrated systems. Presented simulation results show robustness of the proposed topology over process, temperature and supply voltage variations (PVT). The presented FC was used in complex ultra-low power System on-Chip (SoC).

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“…In [1,[8][9][10][11][12][13][14] and [26][27][28], the positive feedback circuit has been added to the core body of the pre-amplifier stage to significantly reduce the comparator response time (delay). However, the positive feedback circuit itself increases both the power consumption as well as the input-referred noise [1].…”

mentioning

confidence: 99%

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Mahmoodian

Dolatshahi

Zanjani

et al. 2022

IET Circuits, Devices & Syst

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In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumption and high‐speed performances. The proposed speed‐up technique for the latch structure controls the threshold voltage (Vth) of the cross‐coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double‐tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double‐tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed‐up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high‐resolution (up to 12 bit) and high‐speed low‐power analogue‐to‐digital converter applications. Moreover, the effects of the non‐ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte‐Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

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Rail‐to‐rail complementary input StrongARM comparator for low‐power applications

Cited by 5 publications

References 8 publications

Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter

Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter

Low-Power CMOS Frequency Comparator

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

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