Radix-Based Digital Calibration Techniques for Multi-Stage Recycling Pipelined ADCs

Chang, Dong-Young; Li, Jipeng; Moon, Un-Ku

doi:10.1109/tcsi.2004.836863

Cited by 39 publications

(20 citation statements)

References 23 publications

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“…For a 2.5b/stage pipeline, the MDAC transfer function of (1) can be modified as follows: (8) This results in an integrated residue PDF after each MDAC stage of (9) Generalizing this result to all multilevel stages we get (10) where M is the number of full bits resolved from a given sub-ADC stage (i.e.…”

Section: B Higher Order Half-bit Redundant Pdf Residue Shapingmentioning

confidence: 99%

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

Guerber

Gande

Moon

2012

IEEE Trans. Circuits Syst. I

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Abstract-An analysis of the statistics of multistage (pipeline, SAR, and algorithmic) ADCs with redundancy is performed and the ability to achieve an extra 6 dB of resolution in ADCs with half-bit redundancy is shown due to probability density function (PDF) residue shaping. This paper classifies redundancy techniques to show that only some have properties leading to statistical resolution improvements. When properly implemented, resolution gains are maintained even in the presence of large sub-ADC nonlinearity. ADC design criteria for maximizing these resolution increases through PDF residue shaping are described including improved back-end ADCs, stage comparator offset bounds, and the use of scaled conventional restoring with Z added levels (CRZ) stage redundancy. PDF residue shaped structural improvements are also quantified in relation to ideal and nonideal traditional multistage ADC structures.

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Section: B Higher Order Half-bit Redundant Pdf Residue Shapingmentioning

confidence: 99%

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

Guerber

Gande

Moon

2012

IEEE Trans. Circuits Syst. I

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“…However, these existing approaches suffer from various penalties. For example, the earliest evolving foreground calibration discussed in [22], [23] requires switching the precise analog circuitry in and out of the pipeline to connect it to a special set of input signals, which adds overheads to the analog front-end by introducing additional capacitances and/or shortening effective conversion time. The dithering-based digital calibration presented in [15], [24] suffers from slow convergence speed and relatively low accuracy due to limited dithering magnitude and strong interference from the input signal, which impede its spread in applications that support intermittent operation.…”

Section: Digital Calibrationmentioning

confidence: 99%

“…By adopting an 1-bit redundancy pipeline stage, the actual bit-weight measurement can be performed by applying a single zero input instead of the special set of input signals in traditional implementations [22], [23]. Meanwhile, a complete auxiliary reconfiguration scheme is designed to keep the analog-signal path completely intact and a compact digital algorithm is employed to save hardware resources and power consumption.…”

Section: Digital Calibrationmentioning

confidence: 99%

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Zheng

Wang

et al. 2016

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a highspeed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

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“…This paper proposes a full-speed foreground digital interstage gain calibration technique based on the comparator forcing concept mentioned in [4]- [6]. These techniques described in [4], [5] cannot be used to estimate the gain error for 1.5-bit stage flip-around, 2.5-bit stage, and 3.5-bit stage architectures.…”

Section: Introductionmentioning

confidence: 99%

At speed digital gain error calibration of pipelined ADCs

Ravi

Sarma

Sahoo

2015

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS)

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This paper proposes a full speed digital gain error calibration technique for pipelined ADCs. The calibration takes care of both finite op-amp gain and capacitor mismatch. Unlike previous calibration techniques that use resistor ladder to generate the calibration signal, the proposed technique uses capacitors switching to reference voltages to eliminate the large RC time constants associated with resistor ladder. The proposed technique also facilitates the calibration to happen at full speed overcoming the drawbacks of existing foreground calibration techniques. 12-bit ADCs with first stage resolution of 1.5-bit, 2.5-bit, 3.5-bit, and 2-bit, followed by an ideal back-end ADC were simulated in system level using MATLAB and then at circuit level in Cadence. The circuit simulations incorporate various non-idealities like finite op-amp gain, op amp settling, and capacitor mismatch. Circuit level simulations in Global Foundry's (GF) 55-nm process with an an open loop op amp gain of 50 dB and capacitor mismatch of ±3% show that the calibration method improves the SFDR by more than 30 dB and SNDR by more than 25 dB.

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Radix-Based Digital Calibration Techniques for Multi-Stage Recycling Pipelined ADCs

Cited by 39 publications

References 23 publications

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

At speed digital gain error calibration of pipelined ADCs

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