Radix-16 signed-digit division

Carter, T.M.; Robertson, James E.

doi:10.1109/12.61063

Cited by 25 publications

(9 citation statements)

References 16 publications

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“…In [26] and [28], a similar compromise is reached during base-16 division by generating two base-4 quotient digits per iteration. Steps 6 and 8 select the two base-2 quotient digits while Figure 19.…”

Section: Quotient Digitmentioning

confidence: 98%

Digit pipelined arithmetic on fine-grain array processors

Nagendra

Owens

Irwin

1995

Journal of VLSI Signal Processing

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Abstract. In this paper, we present a novel scheme for performing fixed-point arithmetic efficiently on fine-grain, massively parallel, programmable architectures including both custom and FPGA-based systems. We achieve an O(n) speedup, where n is the operand precision, over the bit-serial methods of existing fine-grain systems such as the DAP, the MPP and the CM2, within the constraints of regular, near neighbor communication and only a small amount of on-chip memory. This is possible by means of digit pipelined algorithms which avoid broadcast and which operate in a fully systolic manner by pipelining at the digit level. A base 4, signed-digit, fully redundant number system and on-line techniques are used to limit carry propagation and minimize communication costs.Although our algorithms are digit-serial, we are able to match the performance of the bit-parallel methods, while retaining low communication complexity. Reconfigurable hardware systems built using field programmable gate arrays (FPGA's) can share in the speed benefits of these algorithms. By using the organization of logic blocks suggested in this paper, problems of placement and routing that exist in such systems can be avoided. Since the algorithms are amenable to pipelining, very high throughput can be obtained.

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Section: Quotient Digitmentioning

confidence: 98%

Digit pipelined arithmetic on fine-grain array processors

Nagendra

Owens

Irwin

1995

Journal of VLSI Signal Processing

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“…Several SRT implementations have been reported, including radix 2 dividers by Knowles [11], Kuninobu [12], Vandemeulebroecke [22], and Zuras [23], radix 4 by Birman [3] and Fandrianto [8], radix 8 by Fandrianto [9] and Prabhu [16], and radix 16 by Carter [5] and Taylor [21]. SRT dividers with simplified quotient-digit selection using operand range restriction have been presented in Ercegovac [6], Montuschi [14], and Srinivas [18].…”

Section: Introductionmentioning

confidence: 99%

Minimizing the complexity of SRT tables

Oberman

Flynn

1998

IEEE Trans. VLSI Syst.

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This paper presents an analysis of the complexity of quotient-digit selection tables in SRT division implementations. SRT dividers are widely used in VLSI systems to compute floating-point quotients. These dividers use a fixed number of partial remainder and divisor bits to consult a table to select the next quotient-digit in each iteration. This analysis derives the allowable divisor and partial remainder truncations for radix 2 through radix 32, and it quantifies the relationship between table parameters and the complexity of the tables. Several techniques are presented for further minimizing table complexity. By mapping the tables to a library of standard-cells, delay and area values were measured and are presented for table configurations through radix 32. Several conclusions are drawn based on this data which impacts optimized SRT divider designs.

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“…The error estimation in [12] is based on Vignes's method [13], but the observations concerning dynamic precision extension maintain their validity even if a different error estimation method, like ours, is used. Researches on hardware implementations for variable precision arithmetic have been reported already many years ago [21], [22], as well as in recent times [35].…”

Section: State Of the Art 2 And Introductionmentioning

confidence: 99%

“…Finally, this work should be integrated with research in variable precision arithmetic [12], [21], [22], [35], in order to implement dynamic precision extension.…”

mentioning

confidence: 99%

Floating-point numbers with error estimates

Masotti

1993

Computer-Aided Design

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Radix-16 signed-digit division

Cited by 25 publications

References 16 publications

Digit pipelined arithmetic on fine-grain array processors

Digit pipelined arithmetic on fine-grain array processors

Minimizing the complexity of SRT tables

Floating-point numbers with error estimates

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