Radiation-Tolerant Digitally Controlled Ring Oscillator in 65-nm CMOS

Abstract

This paper presents a radiation-tolerant digitally controlled CMOS ring oscillator design suitable for All-Digital Phase-Locked Loop (ADPLL) implementations. To address the challenges presented by harsh radiation environments, a wide tuning range oscillator architecture is presented with superior Single-Event Effect (SEE) tolerance. The proposed oscillator circuit is characterized experimentally in a 65 nm technology and shown to achieve a significant reduction in SEE sensitivity up to a Linear Energy Transfer (LET) of 63.5 MeV mg −1 cm 2 , remain free from harmonic oscillation errors under irradiation and withstand a total radiation dose exceeding 1.5 Grad. At the design frequency of 1.28 GHz, the oscillator dissipates 7 mW of power while achieving a phase noise of −105 dBc/Hz at 1 MHz offset, corresponding to a Figure of Merit (FOM) of 159 dB.

Simulation of a ring oscillator operation during γ-ray irradiation using the TID response model of MOSFETs and its experimental verification

“…In Sect. 3, we applied the proposed model to a ring oscillator circuit [16][17][18][19] and confirmed that it can reproduce the changes in circuit characteristics that occur during irradiation. In Sect.…”

Radiation-tolerant all-digital clock generators for HEP applications

“…found for this circuit at the point of failure. The DCRO ADPLL hence failed to obtain lock as soon as the maximum oscillation frequency became insufficient to provide the desired value [8]. The LC DCO in comparison showed a radiation-induced frequency shift of less than 1%.…”

“…This segmentation distributes devices sensitive to charge collection spatially, causing only a small subset to be affected by any given SEE. To further suppress the phase displacement from SEEs, we proposed to add an additional series resistor in series with the output of each unit cell, which provides additional decoupling of unit cells from one another, as reported in [8]. The oscillator provides 9 bit frequency control range with linear tuning characteristics at an LSB size of 3.5 MHz.…”

“…Combined with the much larger bandwidth of this PLL during operation, phase and frequency transients in the oscillator are quickly counteracted by the feedback of the tracking loop. Only at the highest LET Si could transients exceeding the random jitter of the PLL be detected [8]. The cross section of the LC ADPLL is much larger in comparison, and the root causes for this sensitivity in the LC DCO have been identified in the used inductor geometry and the switched-capacitor cells used in the PVT and acquisition banks, as discussed in [6,13].…”

A Single-Event-Hardened Scheme for Ring Oscillator Applied to Radiation-Resistant PLL Microsystems

“…With the continuous reduction in the feature size of integrated circuit devices and the rapid development of the aerospace industry, the phase-locked loop (PLL) operated in the radiation environment is seriously affected by the single-event effect, which cannot be ignored [1,2]. When high-energy particles act on the PLL, it will induce the singleevent effect, which will make the frequency and phase of the output signal of the PLL drift and cause the circuit system function to be abnormal [3][4][5]. Each module of the PLL has a different response to the single-event effect [6,7].…”