Radiation hardness of VA1 with submicron process technology

We present the performance and radiation tolerance of an analog application-specified integrated circuit (ASIC) developed for the engineering model of X-ray charge-coupled device (CCD) camera onboard the next Japanese astronomical satellite. The ASIC has four identical channels and each of them equips a pre-amplifier and two 16 analog-to-digital converters. The 3 mm square bare chip has been packaged into the 15 mm square quad flat plastic. The front-end electronics test proved its power consumption to be 71 mW for the whole chip at the readout pixel rate of 20 kHz. The equivalent input noise was 32 8 0 3 V and the integrated non-linearity was 0.2% throughout its dynamic range of 20 mV. At the integrated test with an X-ray CCD, we put an identical signal to all of four channels and took the average of their outputs. Then the noise performance improved to be 17 9 0 3 V and the energy resolution of Mn K line from 55 Fe reached down to 135 3 eV (full-width at half-maximum). In order to investigate the radiation tolerance against the total ionizing dose effect, the ASIC was irradiated with 200 MeV proton beam at HIMAC/NIRS in Japan. There was no significant degradation of gain and noise performance until the absorbed dose amounted up to 15 krd, which corresponds to 10 years in the planned low earth orbit (LEO). Although the noise suddenly increased at 15 krd, there was no significant increase of the current in the chip and the performance recovered after the annealing at the room temperature for three months. This suggests that the degradation during the test was caused by temporal charge trapping near or at the interface of SiO 2 and Si bulk. Considering that the typical mission lifetime of X-ray astronomical satellites is 10 years, we proved that our ASIC has sufficient radiation tolerance for the use in the LEO.Index Terms-CMOS analog integrated circuits, 16 modulation, total ionizing dose effect, x-ray charge-coupled device (CCD). Fig. 1. Mask layout of MD01 with a size of 3 mm square. It was made through the 0.35 m CMOS process of TSMC. Four identical channels are positioned in vertical direction and they process the signals from an X-ray CCD simultaneously.

Section: Radiation Tolerancementioning

confidence: 85%

Performance of an Analog ASIC Developed for X-ray CCD Camera Readout System Onboard Astronomical Satellite

Nakajima

Matsuura

Anabuki

et al. 2009

“…By July 2003, the peak luminosity achieved was and the total integrated luminosity was 158. 6 . To extract the -violation parameters from the time-dependent asymmetry, the decay vertex positions have to be measured with an accuracy of several tens of micro-meters.…”

Section: Introductionmentioning

confidence: 99%

“…To improve the weak points, we have upgraded the SVD (SVD2) [3], [4] • Improvement of radiation hardness of the front-end electronics by using the VA1TA chip [5] implemented with a 0.35 process technology instead of VA1 chip with a 0.8 process in SVD1 [6], [7]. • Improvement of vertex resolution and tracking efficiency of charged particles especially in low transverse momentum region by reducing the radius of the innermost layer from 30 to 20 mm and by increasing the number of layers from three to four [8].…”

Section: Introductionmentioning

confidence: 99%

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The data acquisition system of the Belle silicon vertex detector (SVD) upgrade

Ishino¹,

R²,

Abe³

et al. 2004

Self Cite

A newly developed data acquisition system (DAQ) for the upgraded silicon vertex detector (SVD2) in the Belle experiment is described. The system consists of 12 PCs connected through PCI I/O boards to 36 flash analog-to-digital converters (FADCs) to read out a system comprising a total of 110 592 strips. It is designed to cope with the increased number of readout channels and the maximum trigger rate of 1 kHz, foreseen in the future operation with higher beam currents. A measurement of the system performance using sparsification algorithm we have developed yields a 1.3-kHz readout rate for a 5% occupancy with less than 5% dead time, which satisfies the requirements on the maximum trigger rate.Index Terms-Belle, data acquisition, silicon vertex detector.

“…It was replaced by the VA1TA chip [3] manufactured by IDEAS (http://www.ideas.no). The VA1TA is implemented in a 0.35 CMOS process, and it is expected to have a stable performance up to a radiation dose of at least 20 MRad [4].…”

mentioning

confidence: 99%

The Belle trigger system with the new silicon vertex detector SVD2

Ziegler¹,

R²,

Abe³

et al. 2004

Self Cite

During the summer shutdown of 2003, the new silicon vertex detector SVD2 was installed in Belle at the KEKB factory and started to take data in October 2003. It provides important improvements in the tracking capabilities and adds new trigger functionality. In addition, a new hardware trigger Level 1.5 was designed and installed that takes advantage of the digitized SVD hit data. The improvement in the Belle trigger system will be important to deal with the increasing luminosity and higher beam currents of the KEKB factory.Index Terms-Belle, KEKB, silicon vertex detector (SVD), trigger, VA1TA.