Radiation Hardening by the Modification of Shallow Trench Isolation Process in Partially Depleted SOI MOSFETs

Peng, Chao; Hu, Zhiyuan; En, Yunfei; Chen, Yiqiang; Lei, Zhifeng; Zhang, Zhangang; Zhang, Zhengxuan; Li, Bin

doi:10.1109/tns.2018.2798295

Cited by 14 publications

(4 citation statements)

References 26 publications

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“…In 2018, Peng et al investigated two radiation-hardening processes for STI, namely Si implantation and STI oxide nitridation, including their impact on nominal electrical characteristics and radiation hardness [57]. It was found that the TID efects of the NMOS devices are sensitive to the STI radiation-hardening process conditions, and there are optimum process conditions to achieve the best efectiveness of radiation hardening.…”

Section: Radiation Hardening Techniquesmentioning

confidence: 99%

Overview on Radiation Damage Effects and Protection Techniques in Microelectronic Devices

Ren,

Zhu,

et al. 2024

Science and Technology of Nuclear Installations

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With the rapid advancement of information technology, microelectronic devices have found widespread applications in critical sectors such as nuclear power plants, aerospace equipment, and satellites. However, these devices are frequently exposed to diverse radiation environments, presenting significant challenges in mitigating radiation-induced damage. Hence, this review aims to delve into the intricate damage mechanisms of microelectronic devices within various radiation environments and highlight the latest advancements in radiation-hardening techniques. The ultimate goal is to bolster the reliability and stability of these devices under extreme conditions. The review initiates by outlining the spectrum of radiation environments that microelectronic devices may confront, encompassing space radiation, nuclear explosion radiation, laboratory radiation, and process radiation. It also delineates the potential damage types that these environments can inflict upon microelectronic devices. Furthermore, the review elaborates on the underlying mechanisms through which different radiation environments impact the performance of microelectronic devices, which includes a detailed analysis of the characteristics and fundamental mechanisms of damage when microelectronic devices are subjected to total ionizing dose effects and single-event effects. In addition, the review delves into the promising application prospects of several key radiation-hardening techniques for enhancing the radiation tolerance of microelectronic devices.

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Section: Radiation Hardening Techniquesmentioning

confidence: 99%

Overview on Radiation Damage Effects and Protection Techniques in Microelectronic Devices

Ren,

Zhu,

et al. 2024

Science and Technology of Nuclear Installations

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“…首先, 环栅器件面积较大, 降低了芯片的集成度. 其次, 设计过程中不能直接使用晶圆代工厂提供的工艺设计工具包、知识产权模块以及单元库等 [18,19] [20,21] ; 第二, 优化器件工艺达到减小边缘寄生器件漏电的目的, 例如采用STI场区离子注入技术 [22] 和超陡倒掺杂阱技术 [23]…”

Section: 硅栅极unclassified

Radiation hardening by process technology for high voltage nMOSFET in 180 nm embeded flash process

Chen¹,

Sun²

2022

Acta Phys. Sin.

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Radiation hardened embedded flash technology is widely used in aerospace field. The high voltage nMOSFET is the key device to be hardened as it is the most sensitive device to TID effect. This study using STI sidewall implantation method to harden 5V nMOSFET for 180nm eFlash process. Through the study of the TID response of the device, two problems emerged in this hardening technology. Firstly, the hardening ions is implanted after STI trench etching, the doping profile is impacted by the following thermal process, results in lower doping concentration at STI edge. Device failed due to high leakage current after 100k rad(Si) radiation. Secondly, the hardening ions that implanted in drain region reduce the breakdown voltage of PN junction at drain side. Device cannot satisfy the actual requirement in the circuit. To solve these problems, we propose a new device hardening methodology called partial channel ion implantation. Compare to previous methodology, to reduce the doping redistribution effect, we adjust the hardening ion implantation to post the oxidation of gate oxide. Moreover, an extra mask is introduced to define the hardening implantation region to avoid ion implantation at the drain side of the device. Therefore, the drain breakdown voltage would not be influenced by hardening implantation. By using this new hardening technology for high voltage NMOS, the device could maintain the typical design of strip-type gate. The hardening methodology is compatible with general process technology and do not influence the electrical parameters of the device obviously. Results show that with the partial channel ion implantation methodology, the drain leakage of the device is keep at pico-ampere level after 150k rad(Si) radiation. That is five orders of magnitude lower than previous STI implantation hardening technology.

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“…Process level TID countermeasures 1) Oxide hardening techniques: Most Radiation Hardening By Process (RHBP) techniques target mostly oxide enhancements [12]- [16].The implantation of holes or electrons into oxides [12] has been found useful to reduce the V th shift induced by TID radiations. The mechanism behind this technique can be the direct implantation of elements into the oxide such as Al, Si, P, F [13] [14], or creating a thin layer of such materials in order to isolate the TID sensitive parts of the circuit such as the STI [15]. These studies also suggest that the quality of the doping profile is not only limited to the implant particle but additionally to the implantation conditions and thermal control of the procedure.…”

Section: Tid Countermeasuresmentioning

confidence: 99%

X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective

Tebina

Zergainoh

Maistri

2022

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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With the emergence of a novel fault injection technique based on nanofocused X-Ray beams, these attacks have been proven feasible even when using simple laboratory X-Ray sources. X-Rays can induce parametric shifts in MOS components, mostly at the level of oxides: if properly controlled, these shifts lead to reversible stuck-at faults. It is therefore established that X-Rays can indeed be considered a threat that needs to be addressed in the future when designing secure circuits. In this paper, we discuss how countermeasures issued from the state of the art can be exploited to mitigate or resist against this novel attack.

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Radiation Hardening by the Modification of Shallow Trench Isolation Process in Partially Depleted SOI MOSFETs

Cited by 14 publications

References 26 publications

Overview on Radiation Damage Effects and Protection Techniques in Microelectronic Devices

Overview on Radiation Damage Effects and Protection Techniques in Microelectronic Devices

Radiation hardening by process technology for high voltage nMOSFET in 180 nm embeded flash process

X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective

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