Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application

Peng, Chunyu; Huang, J.; Liu, Changyong; Zhao, Qiang; Xiao, Songsong; Wu, Xiulong; Lin, Zhiting; Chen, Junning; Zeng, Xuan

doi:10.1109/tvlsi.2018.2879341

Cited by 110 publications

(49 citation statements)

References 22 publications

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“…To mitigate SNUs or even DNUs, many designs of SRAM cells [4,[6][7][8][9][10][11][12][13][14][15] have been proposed by using the Radiation Hardening By Design (RHBD) approach. RHBD, which is also used for designing latches [16][17] and flip-flops [18][19][20], can effectively mitigate the impact of radiation particles on SRAM cells.…”

Section: Introductionmentioning

confidence: 99%

“…Since the 6T cell cannot tolerate SNUs, many hardened SRAM cells have been proposed for reliability improvement. Typical SNU hardened cells include ST10T [4], NASA13T [6], RHD12T [7], NS10T [8] and RSP14T [9]. Typical DNU hardened cells include RH12T [10] and DNUSRM [11].…”

Section: Introductionmentioning

confidence: 99%

“…(1) Some SRAM cells cannot self-recover from any SNU, such as ST10T [4] and NASA13T [6]. Some SRAM cells can self-recover from SNUs only for a part of internal nodes, such as RHD12T [7], NS10T [8] and RSP14T [9]. Meanwhile, some SRAM cells cannot self-recover from any DNU, such as ST10T [4] and NASA13T [6], and some SRAM cells can self-recover from DNUs only for a part of node pairs, such as RHD12T [7], NS10T [8], RSP14T [9] and RH12T [10].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

Dou

Yan

Zhou

et al. 2020

2020 IEEE International Test Conference in Asia (ITC-Asia)

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In this paper, a highly reliable SRAM cell, namely SESRS cell, is proposed. Since the cell has a special feedback mechanism among its internal nodes and has more access transistors compared to a standard SRAM cell, the SESRS cell provides the following advantages: (1) it can self-recover from single node upsets (SNUs) and double-node upsets (DNUs); (2) it can reduce power consumption by 49.78% and silicon area by 7.92%, compared with the only existing SRAM cell which can self-recover from all possible DNUs. Simulation results validate the robustness of the proposed SESRS cell. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed SESRS cell can reduce read access time by 61.93% on average.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

Dou

Yan

Zhou

et al. 2020

2020 IEEE International Test Conference in Asia (ITC-Asia)

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“…The well potential of transistor is also affected by parasitic resistance, external voltage, doping concentration and other factors [14,15,16,17]. With using the technology of radiation harden by design (RHBD) [18,19,20,21], the charge collection can be effectively mitigated by introducing the guard ring contact in triple-well CMOS process [22]. Recently Zhenyu Wu found that reducing the distance between NMOS transistor and N-well can reduce N-hit SET pulse width [23].…”

Section: Introductionmentioning

confidence: 99%

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS

Zhao

Peng

Liu

et al. 2019

IEICE Electron. Express

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N-well doping concentration plays an important role in singleevent transient (SET) characteristic of transistors. While adjusting the Nwell doping parameter within a proper range, it has little effect on the basic electrical performance of P-type MOSFET. The physical mechanism of well doping effects on the SET of PMOS is observed. The collapse and recovery of N-well potential, which are the critical factors that influences the SET pulse width, are analyzed by TCAD simulations. The result shows that well doping concentration could affect not only the rate of well potential recover to its equilibrium value, but the potential gradient induced by localized collapse of N-well potential between ion-strike path and source. Energy band analysis is also carried out under the triple well structure, and results show that an increase in well doping concentration will elevate the barrier of reverse-biased P-N junction and therefore cause the accumulation of holes in well, elevating the well potential, and consequently, inhibiting the parasitic bipolar amplification effect.

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“…The radiation hardened 14T cell increases resilience to both single and multiple event upsets, due to the charge distribution among OFF-transistors. 14T memory cell optimizes speed and power over 12T memory cell [9].This paper is divided into the five sections. Section I is introduction, Section II explains about the different RHBD memory cell schematics with operation.…”

Section: Introductionmentioning

confidence: 99%

Design And Analysis Of RHBD Memory Cells And 4x4 RHBD 10T Memory Cell Architecture

Chaitanya¹,

Kannan²

2019

IJITEE

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CMOS technology plays an important role in the modern electronics world. CMOS technology also plays significant role in aerospace applications. To store data, memories are widely used as the medium in aerospace applications. SRAM cells are the memories made by the CMOS technology. The most vital issues faced by memories are due to single event upsets (SEUs) which are induced by radiation particles. The SEU’s due to increase in densities and SEU’s. There is a decrease in critical charge and supply voltage in CMOS process technology. There is a need for a technique which can to tolerate these SEU’s in such aerospace applications. Which are in the environment of complex celestial radiation? The technique which is considered for such environment is radiation-hardened by design (RHBD) with soft error robustness. This paper aims at is proposing an area efficient and high reliable RHBD memory cell for the above said application using 45nm technology in Cadence Tool. Depending on power, write/read time, the layout area of 14T, 12T and 10T RHBD memory cells and their performance on power for read/write operations are observed. A comparative study is also done on these memory cells based the parameters considered.

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Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application

Cited by 110 publications

References 22 publications

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors

Physical mechanism study of N-well doping effects on the single-event transient characteristic of PMOS

Design And Analysis Of RHBD Memory Cells And 4x4 RHBD 10T Memory Cell Architecture

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