Radiation hard 1.0μm CMOS technology

Lee, K. H.; Desko, J.C.; Kohler, R.A.; Lawrence, Cris W.; Nagy, W.J.; Shimer, J.A.; Steenwyk, S. D.; Anderson, Richard E.; Fu, J.S.

doi:10.1109/tns.1987.4337498

Cited by 29 publications

(5 citation statements)

References 7 publications

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“…With all one's or alternate one's and zero's (denoted as CB or "checkerboard" in the When an alternate pattern of one's and zero's is stored in the registers, the measured saturation cross section was 4.5 x 10-4 cm2. This is in good agreement with the average cross section of the one's and zero's state, 4.1 x 10-4 cm2, and confirms that the "golden chip" test procedure is measuring upsets in the D-latches and not other circuitry. for all one's, almost a factor of three larger than the measured saturation cross section for the Rev A parts.…”

Section: Resultssupporting

confidence: 81%

“…It has been intentionally designed to withstand severe radiation environments including SEU [3]. The part is fabricated at AT&T Allentown in a 1.25-pm 2-level metal radiation hardened technology [4] and is immune to latchup due to the structure of the technology. The totaldose radiation tolerance of 64K and 256K SRAMs fabricated in this technology have been discussed previously [5].…”

Section: Introductionmentioning

confidence: 99%

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SEU characterization and design dependence of the SA3300 microprocessor

Sexton

Treece

Hass

et al. 1990

IEEE Trans. Nucl. Sci.

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The SEU vulnerability of the SA3300 16-bit microprocessor has been characterized, and the effects of two different design revisions on error rate have been explored. We found that the threshold for upset depends on the data pattern written into the general purpose registers. With all bits in the general purpose registers set to logic one, a design with 2-pm n-. and p-channel transistor lengths had a threshold LET of 35 MeVcm2/mg at 25°C and 4.5 volt operation. With all zero's stored in the registers the upset threshold increased by more than a factor of two to 83 MeVcm2/mg. A second design revision, with 1.25-pm and 1.75-pm n-and p-channel transistor lengths, respectively, was more vulnerable to upset, but exhibited a smaller dependence on logic state. Measured threshold LET was 23 and 35 MeVcm2/mg with all one's and all zero's, respectively. Microprobe measurements using a pulsed Nd:YAG laser suggest that the observed pattern dependence for both design revisions is due to bipolar photocurrent in a vertical n+pn transistor. A slight temperature dependence was observed in both design revisions. This is consistent with the use of oversized restoring transistors to minimize SEU vulnerability rather than polysilicon feedback resistors. More recent data show thresholds above 120 MeV-cmz/mg with 80 kn feedback resistors.

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Section: Resultssupporting

confidence: 81%

Section: Introductionmentioning

confidence: 99%

SEU characterization and design dependence of the SA3300 microprocessor

Sexton

Treece

Hass

et al. 1990

IEEE Trans. Nucl. Sci.

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“…The former mechanism is referred to as "number" fluctuations while the latter is termed "mobility" fluctuations. 4 Data from narrow-channel MOSFETs confirm that both effects can be important [19]. In general, noise studies on n-channel MOSFETs tend to agree with predictions that neglect the mobility fluctuation mechanism while studies on p-channel MOSFETs do not [14].…”

Section: Trapping Model For the Noisementioning

confidence: 92%

“…The processing of these wafers has been described elsewhere [1,2]. Measurements have also been performed on devices from two additional wafers, one from AT&T's 1-µm radiation hardened technology (Lot 11370, Wafer 50) [4] and the other from Sandia's 3-µm "mod B" radiation tolerant technology (Lot DE152D, Wafer 22) [5]. Devices from this latter wafer have identical dimensions to those listed above and an oxide thickness of 45 nm.…”

Section: Samplesmentioning

confidence: 99%

Physical basis for nondestructive tests of MOS radiation hardness

Scofield

Fleetwood

1991

IEEE Trans. Nucl. Sci.

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measurements have been extended to include temperatures in the range 80-300K. These results are used to expand upon a trapping model of the noise. The evidence suggests that the noise and the oxide-trap charge are both influenced by the preirradiation density of oxygen vacancies in the SiO 2 [2]. We have found that the 1/f noise and channel resistance of unirradiated nMOS transistors from a single lot with various gate-oxide splits closely correlate with the oxide-trap and interface trap charge, respectively, following irradiation. The 1/f noise is explained by a trapping model, while the variations in channel resistance are explained by scattering from interface-trap precursor defects. It appears that both noise and channel mobility measurements may be useful in defining nondestructive hardness assurance test methods for devices fabricated from a single technology. It may be difficult to use either for making cross-technology comparisons. Finally, during the course of this study it was found that process techniques that improve the radiation hardness of MOS devices at room temperature can greatly reduce the 1/f noise of MOS devices at cryogenic temperatures. * We also demonstrate a striking correlation between the preirradiation channel resistance of MOS transistors and their postirradiation interface-trap charge [3]. We have developed a model that relates the preirradiation 1/f-noise to the net radiation-induced oxide charge-trapping efficiency [2], and a model that relates the preirradiation channel mobility to radiation-induced interface trap generation efficiency [3]. We conclude that, even before a device is irradiated, carrier-defect interactions evidently reveal a great deal of information about the radiation hardness of MOS devices. Implications for hardness assurance testing are discussed.

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“…Comparison of the SEU data of the TC17-and the TA670-provided scaling effect derived solely from the lateral dimensional reductions, since both TC17 and TA670 were fabricated with the same 1-pm process. 5…”

Section: Ta670 Ano the Modified Ta670 With Thicker Gate Oxidementioning

confidence: 99%

Processing-Enhanced SEU Tolerance in High Density SRAMs.

Fu¹,

Weaver²,

Browning³

et al. 1988

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Radiation hard 1.0μm CMOS technology

Cited by 29 publications

References 7 publications

SEU characterization and design dependence of the SA3300 microprocessor

SEU characterization and design dependence of the SA3300 microprocessor

Physical basis for nondestructive tests of MOS radiation hardness

Processing-Enhanced SEU Tolerance in High Density SRAMs.

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