Radiation Experiments on a 28 nm Single-Chip Many-Core Processor and SEU Error-Rate Prediction

Vargas, Vanessa; Ramos, Pablo; Ray, Vincent; Jalier, Camille; Stevens, R.W.; Dinechin, Benoît Dupont de; Baylac, M.; Villa, Francesca; Rey, Solenne; Zergainoh, Nacer-Eddine; Mehaut, Jean-François; Velazco, Raoul

doi:10.1109/tns.2016.2638081

Cited by 22 publications

(16 citation statements)

References 16 publications

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“…In the authors' previous work [8] was presented an SEU error-rate prediction method that combines radiation experiments with fault-injection. The method was evaluated on the same target device (MPPA-256) implementing a parallel matrix multiplication running on bare-metal without OS.…”

Section: Resultsmentioning

confidence: 99%

“…Regarding the reliability, it was considered that applications are intended to be used in the avionics domain for commercial airlines, being the neutron flux at 35,000 ft of altitude (φ ev =2993.2 n/cm 2 /h) with a system life time of 50,000 h. The σ Static = 12.71× 10 −9 cm 2 /device was taken from a previous work [8]. Table 7 summarizes the estimated failure rates per hour computed using (3) at avionics altitude for both applications under three scenarios: without the fault-tolerance approach, NMR-MPar running with the supervisor and implemented with NMR-MPar running without the supervisor device.…”

Section: Discussionmentioning

confidence: 99%

“…In spite of the manufacturing efforts, there are some areas that remain vulnerable to the effects of natural radiation. A few interesting works dealing with the sensitivity of multi-core and many-core processors can be found in the literature [4][5][6][7][8]. Results showed that complementary mitigation techniques are required for the widespread use of COTS processors in safety-critical domains such as avionics.…”

Section: Introductionmentioning

confidence: 99%

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NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

et al. 2018

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The N-Modular Redundancy and M-Partitions (NMR-MPar) fault-tolerance approach can be used to improve the reliability of embedded systems that are based on Commercial-Off-The-Shelf (COTS) multi-/many-core processors, especially those with a non-critical time constraint allowing a diminution in performance to gain reliability by maintaining power consumption. Typically, mixed-criticality systems, such as avionics or spacecraft, comply with these requirements.

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Section: Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

et al. 2018

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“…e evaluation of the device's dynamic response shows that, by enabling the cache memories, it is possible to gain in performance of the application without compromising reliability. Additionally, the results suggest that ECC and interleaving implemented in the static memories of the targeted clusters are very effective to mitigate SEUs since all detected events were corrected [15].…”

Section: Related Workmentioning

confidence: 94%

Assessing the Static and Dynamic Sensitivity of a Commercial Off-the-Shelf Multicore Processor for Noncritical Avionic Applications

Ramos

Vargas

Zergainoh

et al. 2018

Journal of Nanotechnology

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The present work assesses the radiation sensitivity of an affordable and performant COTS multicore processor for noncritical avionic applications. The target device is the Epiphany E16G301 multicore manufactured in 65 nm CMOS which integrates 16 processor cores. This device was selected due to its high performance, low power consumption, and affordability, allowing general public accessing to parallel computing. Additionally, the E16G301 is the coprocessor for parallel processing of the Parallella platform, which was considered by NASA researchers for onboard health management of the DragonEye UAS. The evaluation of the device is done using quantitative theory by means of radiation experiments with 14 MeV neutrons to emulate the effects of high-energy neutrons present at avionic altitudes. Static and dynamic cross sections are obtained to evaluate the intrinsic sensitivity of the device as well as its dynamic response. Results show that the failure rate of the E16G301 running a matrix multiplication as application reaches level D of the DO-178B/C guideline, being the device well suited for minor failure conditions of avionic applications.

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“…A bit-flip in the storage elements, including D flipflops (DFFs) and various types of memory, has different impacts on the vision processor performance. Directly hardening the vision processor via mitigation techniques [10,11,12] will lead to an extra chip area and power consumption. So we should initially evaluate the SEU sensitivity of the storage elements and identify the critical elements.…”

Section: Introductionmentioning

confidence: 99%

Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors

Zhang

et al. 2019

IEICE Electron. Express

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This paper proposes novel single event upset (SEU) failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. To automatically evaluate the SEU failure probability and identify all the critical elements in a processor, complementary fault injection methods based on logic circuit simulator and Perl script are proposed. These methods can be used to randomly inject faults into D flip-flops (DFFs) and various types of memory at the register transfer level (RTL) as well as to evaluate the vision processor performance. Based on the evaluation results, an accurate periodic scrubbing technique is proposed to increase the processor availability. The results denote that the peak availability of the processor over a period of one year can be improved from 18% to 99.9% after scrubbing the RISC program memory for a period of 10 4 s. Therefore, we can improve the fault-tolerance performance of a vision processor while avoiding unnecessary area and power costs using techniques ranging from evaluation to mitigation.

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Radiation Experiments on a 28 nm Single-Chip Many-Core Processor and SEU Error-Rate Prediction

Cited by 22 publications

References 16 publications

NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

Assessing the Static and Dynamic Sensitivity of a Commercial Off-the-Shelf Multicore Processor for Noncritical Avionic Applications

Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors

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