Radiation Dose Effects in Trigate SOI MOS Transistors

Colinge, Jean–Pierre; Orozco, A.; Rudee, J.; Xiong, Wenjing; Cleavelin, C.R.; Schulz, T.; Schrüfer, K.; Knoblinger, G.; Patruno, P.

doi:10.1109/tns.2006.885841

Cited by 47 publications

(29 citation statements)

References 8 publications

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“…Indeed, [16], [17] have demonstrated the fin width dependence of the TID response of multiple-gate FETs up to the 10 kGy range [16], [17], [31], [32]. Such devices should withstand high amount of TID even under normal operating conditions (biased).…”

Section: Soi Finfet/nanowire Technologymentioning

confidence: 99%

Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments

Gaillardin

Girard

Paillet

et al. 2013

IEEE Trans. Nucl. Sci.

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Section: Soi Finfet/nanowire Technologymentioning

confidence: 99%

Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments

Gaillardin

Girard

Paillet

et al. 2013

IEEE Trans. Nucl. Sci.

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“…The introduction of multiple gates creates an environment where the control of the electrostatic potential induced in the fin and the isolation regions from the lateral gates largely defines the TID response of the whole device. Therefore, wide-fin devices have shown reduced hardness when compared to narrower fin SOI devices [44], [45]. By contrast, in bulk FinFETs, the opposite is true where wide fins increase the TID hardness [46].…”

Section: Finfets and Other Multigate Architecturesmentioning

confidence: 99%

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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-From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory.Index Terms-2-D semiconductor, carbon, CMOS, deep submicrometer, FinFET, graphene, MoS2, resistive random access memory (RRAM), silicon-on-insulator (SOI), thin film, total ionizing dose (TID), ultrathin buried oxide (UTBOX).

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“…In the both of p-channel [17] and n-channel [18] MOSFET case, it was clarified that the Coulomb scattering by irradiation-induced charged oxide traps and SiO 2 /Si interface traps is the dominant degradation factor for the hole mobility. It is also well-known that thermal recovery of the device performance helps identifying the degradation mechanism of the devices by irradiation [19].…”

Section: Introductionmentioning

confidence: 99%

Thermal recovery process of electron irradiated Si_1‐xC_x source/drain n‐MOSFETs

Takakura

Hori

Yoneoka

et al. 2015

Phys. Status Solidi C

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In this study, the performance degradation by electron irradiation and the thermal recovery process of Si0.99C0.01 source/drain (S/D) n‐MOSFETs are reported. The electron mobility is 15% enhanced by 1%‐C doping in the S/D stressor region. The electron mobility is degraded by 2‐MeV electron irradiation, but the relative change was the same irrespective of C doping and electron fluence. This fact indicates that tensile‐strain relaxation by displacement damage in the Si:C stressors is not significantly impacting the mobility degradation by electron irradiation. Evidence is given that increased scattering in the channel is the main cause of mobility degradation by 2‐MeV electron irradiation. In addition, it is shown that for a fluence of 5x1017 e/cm2, the electrical performance is recovered by thermal annealing. After 323 K for 15 min annealing, the mobility amounts to 95% of the pre‐irradiation value. In the case of Si0.7Ge0.3 S/D p‐MOSFETs, it has been shown before that the device performance is recovered to the same degree for the same irradiation/thermal annealing conditions of this study. CMOS circuits are fabricated by a combination of n‐MOSFETs and p‐MOSFETs, therefore, it can be confirmed that strained CMOS devices using Si:C S/D n‐MOSFETs and SiGe S/D p‐MOSFETs, respectively, can operate in the radiation environment studied here. (© 2015 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Radiation Dose Effects in Trigate SOI MOS Transistors

Cited by 47 publications

References 8 publications

Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments

Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Thermal recovery process of electron irradiated Si_1‐xC_x source/drain n‐MOSFETs

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Radiation Dose Effects in Trigate SOI MOS Transistors

Cited by 47 publications

References 8 publications

Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments

Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Thermal recovery process of electron irradiated Si1‐xCx source/drain n‐MOSFETs

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Product

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Thermal recovery process of electron irradiated Si_1‐xC_x source/drain n‐MOSFETs