Radiation characterization of a dual core LEON3-FT processor

Sturesson, Fredrik; Gaisler, J.; Ginosar, Ran; Liran, Tuvia

doi:10.1109/radecs.2011.6131334

Cited by 16 publications

(5 citation statements)

References 2 publications

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“…Airbus [52,53] uses the LEON4 high reliable processor board, providing up to 800 million instructions per second (MIPS), as well as the LEON3-based SCOC3 SOC with considerably worse performance. RamonChip [54] implemented one of the most advanced dual-core LEON3-FT devices, namely the GR712RC, which is fabricated on 180 nm complementary metal-oxide-semiconductor (CMOS) and provides up to 200 DMIPS∕million floating-point operations per second (MFLOPS) at 100 MHz, dissipates less than 2 W, and withstands up to 300 krad TID, with SEU tolerance and SEL above 118 MeV ⋅ cm 2 ∕mg. Today, the top LEONbased processor is LEON4-FT (e.g., the GR740 at 65 nm), which includes a quad-core operating at 250 MHz and delivering 425 DMIPS per core; this multicore LEON4 targets up to 4300 DMIPS at 800 MHz and supports both asymmetric and symmetric multiprocessing configurations (AMP or SMP).…”

Section: Survey Of Processing Platforms For Space Applicationsmentioning

confidence: 99%

High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation

Lentaris¹,

Maragos²,

Stratakos³

et al. 2018

Journal of Aerospace Information Systems

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Vision-based navigation has become increasingly important in a variety of space applications for enhancing autonomy and dependability. Future missions, such as active debris removal for remediating the low Earth orbit environment, will rely on novel high-performance avionics to support advanced image processing algorithms with substantial workloads. However, when designing new avionics architectures, constraints relating to the use of electronics in space present great challenges, further exacerbated by the need for significantly faster processing compared to conventional space-grade central processing units. With the long-term goal of designing highperformance embedded computers for space, in this paper, an extended study and tradeoff analysis of a diverse set of computing platforms and architectures (i.e., central processing units, multicore digital signal processors, graphics processing units, and field-programmable gate arrays) are performed with radiation-hardened and commercial offthe-shelf technology. Overall, the study involves more than 30 devices and 10 benchmarks, which are selected after exploring the algorithms and specifications required for vision-based navigation. The present analysis combines literature survey and in-house development/testing to derive a sizable consistent picture of all possible solutions. Among others, the results show that certain 28 nm system-on-chip devices perform faster than space-grade and embedded central processing units by 1-3 orders of magnitude, while consuming less than 10 W. Field-programmable gate array platforms provide the highest performance per watt ratio.

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Section: Survey Of Processing Platforms For Space Applicationsmentioning

confidence: 99%

High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation

Lentaris¹,

Maragos²,

Stratakos³

et al. 2018

Journal of Aerospace Information Systems

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“…The latest available NASA crosscutting technology roadmap lists key avionics goals to include improved reliability and fault tolerance, increased autonomy, reduced size, weight, and power (SWaP), and commonality across spaceflight and ground processing systems [25]. Long-duration crewed missions, space-based observatories, and solar system exploration will require highly reliable, fault-tolerant systems.…”

Section: Mission Scenarios and Applicationmentioning

confidence: 99%

“…Advanced avionics technologies and approaches are needed to support these challenging missions. Subsection TA11.1.1 of the Chief Technologists Office Technology Roadmap lists the three areas of flight computing that are critical to next-generation needs for science and exploration to include processors, memory, and high-performance flight software [25]. Scalable, multicore processors, co-processors, and memory that have a range of capabilities for fault tolerance and recovery are needed for use in radiation fields to support an increasingly software-intensive onboard environment.…”

Section: Mission Scenarios and Applicationmentioning

confidence: 99%

Enabling radiation tolerant heterogeneous GPU-based onboard data processing in space

Bruhn

Tsog

Kunkel³

et al. 2020

CEAS Space J

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The last decade has seen a dramatic increase in small satellite missions for commercial, public, and government intelligence applications. Given the rapid commercialization of constellation-driven services in Earth Observation, situational domain awareness, communications including machine-to-machine interface, exploration etc., small satellites represent an enabling technology for a large growth market generating truly Big Data. Examples of modern sensors that can generate very large amounts of data are optical sensing, hyperspectral, Synthetic Aperture Radar (SAR), and Infrared imaging. Traditional handling and downloading of Big Data from space requires a large onboard mass storage and high bandwidth downlink with a trend towards optical links. Many missions and applications can benefit significantly from onboard cloud computing similarly to Earth-based cloud services. Hence, enabling space systems to provide near real-time data and enable low latency distribution of critical and time sensitive information to users. In addition, the downlink capability can be more effectively utilized by applying more onboard processing to reduce the data and create high value information products. This paper discusses current implementations and roadmap for leveraging high performance computing tools and methods on small satellites with radiation tolerant hardware. This includes runtime analysis with benchmarks of convolutional neural networks and matrix multiplications using industry standard tools (e.g., TensorFlow and PlaidML). In addition, a ½ CubeSat volume unit (0.5U) (10 × 10 × 5 cm3) cloud computing solution, called SpaceCloud™ iX5100 based on AMD 28 nm APU technology is presented as an example of heterogeneous computer solution. An evaluation of the AMD 14 nm Ryzen APU is presented as a candidate for future advanced onboard processing for space vehicles.

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“…For example, The SPARC AT697 introduced in 2003 has an operating frequency of 66 MHz, uses triple modular redundancy (TMR) for logic soft error protection, and error detection and correction (EDAC) for memory soft error protection [9] [10]. More recent RHBD processors have reached 125 MHz [11].…”

Section: Introductionmentioning

confidence: 99%

“…For instance, the StrongARM design operates at 160 MHz in a 350-nm process and the 180-nm XScale microprocessor operates at 600 to 900 MHz [11] [12]. The 90-nm versions of the XScale microprocessors achieved 1.2 GHz with the cache performance being even higher [13] [14].…”

Section: Introductionmentioning

confidence: 99%

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

Clark

Patterson

Ramamurthy

et al. 2016

IEEE Trans. Comput.

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A radiation hardened by design embedded microprocessor is presented. The design uses multiple approaches to minimize the performance reduction from hardening, while simultaneously limiting the power increase. The speculative portions of the pipeline are protected by microarchitecture approaches, i.e., the speculative pipeline is dual redundant, whereby instructions that have errors in one copy cause a pipeline restart-only matching results commit to architectural state. The register file is dual redundant with mechanisms for correction using one copy whose parity is correct. The data cache memory is write-through, allowing protection with parity. The remaining architectural state is protected via hardened circuits. These are implemented with self-correcting triple mode redundant (TMR) flip-flops and TMR logic. The design, implemented here on a 90-nm bulk CMOS process, achieves unprecedented single event effects hardness and 400+ MHz operating frequency at less than 500 mW power consumption. The main constituent circuit hardening approaches have been fabricated and tested separately. Broad beam testing of the constituent circuits has resulted in no uncorrectable soft errors below 100 MeV-cm 2 /mg LET EFF . We describe the CAD flows used to ensure node separation to achieve high immunity to multiple node charge collection and discuss the relative costs of the chosen hardening techniques.Index Terms-Radiation hardening by design (RHBD); microprocessor; cache memory; total ionizing dose; single event transients, soft error mitigation, single-event effects.

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Radiation characterization of a dual core LEON3-FT processor

Cited by 16 publications

References 2 publications

High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation

High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation

Enabling radiation tolerant heterogeneous GPU-based onboard data processing in space

An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits

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