Race-condition-aware clock skew scheduling

Abstract

The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and delay insertion (for resolving the race conditions) may lead to further clock period reduction. However, the interactions between clock skew scheduling and delay insertion have not been well studied. In this paper, we provide a fresh viewpoint to look at this problem. A novel approach, called race-condition-aware (RCA) clock skew scheduling, is proposed to determine the clock skew schedule by taking the race conditions into account. Our objective is not only to optimize the clock period, but also to heuristically minimize the required inserted delay. Compared with previous work, our approach has significant improvement in the time complexity.

PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess

“…While the traditional approach [15] considers an ASIC environment where any arbitrary delay is realizable, our algorithm targets FPGAs, is aware of discrete delay steps, process variation margins that limit both the minimum and maximum delay that can be assigned to a node, and the possibility that delay padding may fail due to these margins. To our knowledge, this is the first time delay padding has been applied to FPGAs.…”

“…In each iteration of assign skew(), the optimum period and skews determined with the approach in [6] are stored in a solution array, and all critical hold time edges are appended into a list of currently deleted edges [15]. In each iteration, the combinational LUTs on each critical edge are identified and put into arrays with find deleted edge nodes().…”

“…2) Integrated delay padding scheme with CSS to further optimize performance. Past work ( [14], [15], [16], [17]) uses either LP or graph theory to solve CSS. However, these techniques apply only to ASICs, and assume padded delays are continuous.…”

Multi-parameter clock skew scheduling

“…To do that, a set of constraints is given by setup-time and hold-time requirements, while the objective is to optimize either the clock period or the timing yield [1][2][3][4][5][6][7]. This problem can be formulated as a special kind of linear programming known as minimum cost-to-time ratio cycle problem, or minimum ratio cycle problem (MCR).…”

Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays

“…Minimization of the clock period with methods like [4,5] are critical especially when circuit designs are performance dominant. However, due to the increasing process variations in nanometer technology, yield has become more and more important than performance in today's integrated circuits design.…”