Quasi-One Dimensional Conduction in Polycrystalline Silicon Nano Wire

Abstract

Electrical conduction characteristics of polycrystalline silicon (poly-Si) nano wire between temperature of 300 K and 2 K are reported. The nano wire, 5-8 nm wide, L0-20 nm high and grain length of around 100 nm is fabricated by the self-aligned confinement of a 100 nm wide and 100 nm deep trench formed in silicon substrate. The resistance increases with the reduction of temperature, which might be attributed to the weak localization phenomena due to the quasione dimensional structure of the nano wire. The conductance exhibits a gap of about 30 mV below 1.0K, which is attributed to a barrier height of about 1 meV at the grain boundary of the poly-Si layer.

SiO 2 -enhanced synthesis of Si nanowires by laser ablation

“…Si nanowires have been synthesized by different methods, such as scanning tunneling microscopy 10,11 and photolithography techniques combined with etching. [12][13][14] Recently, Si nanowires have been successfully synthesized by a novel method, namely, laser ablation of metal-containing Si targets. [15][16][17] From previous investigations, 15,18 it has been suggested that metal silicide nanoparticles act as the critical catalyst during nanowire deposition assisted by laser ablation.…”

Silicon nanowires grown by metal-catalyst-free VLS process

“…Silicon nanowires are one of the most important 1D nanomaterials under development, and have recently attracted further attention because of their high compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology, leading to possible integration with electronic devices [5][6][7]. Several methods have been used to prepare Si nanowires, including chemical vapor deposition [8][9], solution phase synthesis [10], lithography related etching methods [11], photolithography techniques [12][13][14], and scanning tunneling microscopy [15][16]. The vapor-liquid-solid (VLS) method that uses gold (Au) as a catalyst is one of the most prevalent approaches to Si nanowire synthesis [17][18][19][20].…”

Cu/SiO 2−x nanowires with compositional modulation structure grown via thermal evaporation

“…Various techniques [1][2][3][4][5][6][7][8][9][10] have been developed for synthesizing nanowires including semiconductor nanowires, oxide nanowires, and metal nanobelts. [11][12][13][14][15][16][17] In order to manufacture electronic devices using nanowires, interfaces accommodated with functional variation in a single nanowire have been made.…”