Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) Using II–VI Barrier Layers

Gogna

et al. 2015

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This study shows the use of a high-j ZnS/ZnMgS/ZnS heteroepitaxial tunneling layer in an InGaAs field-effect transistor. Experimental fabrication and simulation of this semiconductor structure show promise of reducing threshold voltage variation by replacing silicon and hafnium oxides as a gate insulator. The II-VI tunneling insulator is grown on an InGaAs substrate using ultraviolet-irradiated metalorganic vapor-phase epitaxy. GeO x -Ge cladded quantum dots are self-assembled to form the gate material. The gate consists of two self-assembled individually cladded quantum dot layers which allow multilogic behavior. Simulations calculated by solving the Schrödinger and Poisson equations self-consistently confirm experimental I D -V D characteristics and show the electron distribution in an inversion channel/quantum well under different gate voltage bias values.

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Section: Qd Floating Gate Nonvolatile Memorymentioning

confidence: 99%

“…If intermediate states were introduced between 0 and 1, the signals would have additional states to process information more effectively. 2 Such multistate FETs could be used for multivalued logic (MVL) to reduce the number of gates and transistors, 3-9 thereby decreasing power dissipation in digital circuits.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Simulation of InGaAs Field-Effect Transistors with II–VI Tunneling Insulators

Suarez¹,

Gogna

et al. 2015

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“…18 voltage accounting for the carriers in energy minibands (i). Here, the threshold voltage V thi and shift DV thi depend on the concentration of electrons (dependent on V g ); this, in turn, determines the occupancy of several energy mini-bands.…”

Section: Cladded Ge Quantum Dot Channel (Qdc) Sws-fet Structuresmentioning

confidence: 99%

“…19 The formulation is revisited, but the analytical expression for channel carrier density (as a function of Fermi level along the channel) is replaced by a numerical expression derived from the density of states (DOS) in a 3D QDSL. The DOS for a 3D QDSL can be obtained from 3D Kronig-Penny (K-P) analysis, 18,20 and used to create a numerical carrier density function that may be inserted into the integrals over Fermi level and channel potential.…”

Section: Cladded Ge Quantum Dot Channel (Qdc) Sws-fet Structuresmentioning

confidence: 99%

“…The gate insulator may be HfO 2 , which has previously been tried in Ge QDC-FETs. 18 Alternatively, the top half of the GeO x cladding on the uppermost dot shown here can be replaced by a ZnSe layer. This would enable growth of a high-k lattice-matched ZnMgSSe gate insulator layer, resulting in reduced threshold variability because of improved interface state density.…”

Section: Separation Of Semiconducting and Metallic Cntsmentioning

confidence: 99%

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Si and InGaAs Spatial Wavefunction-Switched (SWS) FETs with II–VI Gate Insulators: An Approach to the Design and Integration of Two-Bit SRAMs and Binary CMOS Logic

Jain

Lingalugari

et al. 2015

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Electron wavefunctions are switched spatially from one quantum well to another by varying the gate voltage V g in spatial wavefunction-switched (SWS) field-effect transistors (FETs), which comprise two or more coupled quantum wells serving as the transport channel. This is shown for Si/SiGe and InGaAs/AlInAs quantum well systems. The presence of charge in a particular well or channel is used to encode four states 00, 01, 10, 11. This unique property is used for two-bit processing, resulting in compact two-bit static random-access memory devices. Experimental data including capacitance-voltage peaks in Si and InGaAs multiple quantum well SWSFETs has verified the SWS phenomenon. Replacing quantum wells by an array of cladded quantum dots, forming a quantum dot superlattice (QDSL) layer, enhances the contrast and noise margin in SWS-FETs. This paper reports I-V and C-V characteristics for a fabricated twin-drain SWS-quantum dot channel (QDC) FET comprising four layers of self-assembled SiO x -Si quantum dots. SWS-QDC-FETs are shown to be scalable to $9 nm, and comprise four layers of cladded quantum dots with an array of 3 9 3 forming the channel.

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Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Lingalugari

Baskar

et al. 2013