Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Lingalugari, M.; Baskar, K.; Chan, Pik-Yiu; Dufilie, Pierre; Suarez, Ernesto; Chandy, John A.; Heller, E.; Jain, F.

doi:10.1007/s11664-013-2696-7

Cited by 13 publications

(5 citation statements)

References 6 publications

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“…Quantum dots can be assembled in the gate region resulting in quantum-dot gate (QDG) FETs. 18 SiO x -cladded quantum dots of Si and GeO x -cladded quantum dots of Ge behave like a quantum-dot superlattice (QDSL). Energy minibands have been computed in SiO x -Si and GeO x -Ge QDSL using the Kronig-Penney model, 17 treating QDs as an array of artificial atoms of dimension a separated by cladding between two adjacent dots as a barrier of width b.…”

Section: Multibit Sws-based Qd-nvram Two-bit Registers and Two-bit Sramsmentioning

confidence: 99%

Low-Threshold II–VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic

Jain

Saman

Gudlavalleti

et al. 2021

Journal of Elec Materi

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The aim of this paper is to design low-threshold variation, four-state/two-bit Si/SiGe quantum-well n-and p-channel spatial wavefunction-switched fieldeffect transistors (SWS-FETs). This is achieved by incorporating high-k lattice-matched ZnS-ZnMgS gate dielectric layers resulting in low interface charge. Quantum simulations show switching of electron wavefunction from the lower to the upper Si quantum well in the n-channel as the gate voltage is increased. In the p-channel case, the hole wavefunction switches from the upper to the lower SiGe quantum well. The novelty is in the use of highmobility metal-oxide-semiconductor (MOS)-gate modulation-doped (MOD) SWS-FETs. The low-threshold lattice-matched gate insulator SWS-FETs are scalable to sub-7 nm and are compatible with quantum-dot nonvolatile random-access memories (QD-NVRAMs). In terms of multivalued logic (MVL) gates, our circuit simulations using the Berkeley Short-channel IGFET Model (BSIM)-based analog behavioral model (ABM) have shown two-bit/four-state output-input transfer characteristics in SWS-complementary metal oxide semiconductor (CMOS) inverters having two Si/SiGe quantum-well channels. In addition, two-bit static random-access memories (SRAMs) are designed, resulting in significantly reduced FET count and power dissipation. Finally, integration of multivalued SWS-CMOS logic, multibit QD-NVRAM cells, and SWS-based SRAMs and registers is presented.

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Section: Multibit Sws-based Qd-nvram Two-bit Registers and Two-bit Sramsmentioning

confidence: 99%

Low-Threshold II–VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic

Jain

Saman

Gudlavalleti

et al. 2021

Journal of Elec Materi

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“…The threshold voltage shift (Δ V TH ) due to the charges present in the QDs can be expressed as (1) [4]

normalΔ V_{normalTH} = \frac{Q}{C_{CG - FG}} = \frac{\int_{o}^{t_{w}} j false(t false) A d t}{C_{normalCG - normalFG}}

where C CG–FG is the capacitance between the control gate and the QDs in the floating gate, A is the area of the floating gate, and j ( t ) is the current density while performing the Write or Read operation for a duration of t w , which is given in (2) below:

j false(t false) = q \times n_{normaldot} \times N_{normalQD} \times P_{w false\to d}

In (2), q is the charge of an electron, n dot is the number of electrons per dot (bound as well as the electrons trapped at the QDs interface), N QD is the density of QDs, and P w=>d is the tunnelling rate of carriers from the channel (quantum well) to QDs [6]. The amount of charges transferred to the QDs depends on the tunnelling probability of the wavefunctions of the inversion channel ( ψ w ) and the QDs ( ψ d ).…”

Section: Quantum Simulationsmentioning

confidence: 99%

“…These nano‐crystalline/QD flash memories were limited due to non‐uniformity in the QD sizes and inter‐dot spacing. Several efforts are ongoing to improve the performance of QD‐based NVMs (QDNVMs) including the use of metallic nanocrystals [2] and the replacement of uncladded QDs with cladded QDs [3–6].…”

Section: Introductionmentioning

confidence: 99%

“…These nanocrystalline/QD flash memories were limited due to non-uniformity in the QD sizes and inter-dot spacing. Several efforts are ongoing to improve the performance of QD-based NVMs (QDNVMs) including the use of metallic nanocrystals [2] and the replacement of uncladded QDs with cladded QDs [3][4][5][6]. In this Letter, we present a device structure that transforms NVMs into nanosecond, low-power NVRAMs, by directly accessing the floating gate using the QD access channel (QDAC) via drain D2.…”

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confidence: 99%

“…Quantum simulations showing tunnelling of electrons from inversion channel to bottom QD floating gate layer atV G = 0.8 VThe threshold voltage shift (ΔV TH ) due to the charges present in the QDs can be expressed as (1)[4] …”

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confidence: 99%

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QD floating gate NVRAM using QD channel for faster erasing

et al. 2018

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A new pathway to design floating gate quantum dot (QD) non-volatile RAM (QDNVRAM) cells that possess high-speed low-voltage Erase capabilities not possible with conventional floating gate NV memories is presented. This is achieved by directly accessing the QD floating gate layer with an additional drain (D2) during the Erase operation. Experimental data on fabricated long-channel (10 μm/14 μm) QDNVRAM cell shows 'Erase' pulse duration of ∼4 μs at voltage of about 10 V using drain D2 which is over two-order smaller than the 'Write' pulse value. Quantum mechanical simulations are also presented. QDNVRAM fabrication process is compatible with CMOS processing.

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