Quantization Noise Suppression in Fractional-$N$ PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider

Ren

IEICE Electron. Express

2020

A wideband low-jitter phase-locked loop (PLL) is proposed to provide high performance clocks for the transceivers. The ring voltagecontrolled oscillator (Ring-VCO) is a key component of a PLL, which directly determine the out-band phase noise and output frequency range of the PLL. Therefore, a low phase noise two-stage Ring-VCO with a novel delay cell is proposed to help achieve a wideband low-jitter PLL. An accumulation-mode MOS (AMOS) varactor pair is adopted in the delay cell to improve the fine tuning linearity. Moreover, an additional AMOS varactor pair is employed to reduce the VCO gain variation in the coarse tuning process and enhance the tolerance in temperature and voltage variations. Implemented in a conventional TSMC 180 nm CMOS process, the proposed Ring-VCO can tune from 0.73 to 1.92 GHz and the worstcase phase noise at 1 MHz offset is −102 dBc/Hz. The output frequency range of the proposed PLL is 0.06-1.92 GHz and the RMS jitter is less than 3.8 ps over the whole working band.

Section: The Proposed Wideband Low-jitter Pllmentioning

confidence: 99%

A wideband low-jitter PLL with an optimized Ring-VCO

Ren

IEICE Electron. Express

2020

Lecture Notes in Computer Science

“…According to divisor, it can be divided into integer divisor and fractional-n divisor. The fractional-n frequency divider can be constructed by using two integer dividers, a divide-by-n divider and a divide-by-(n+1) divider [1][2].…”

Section: Introductionmentioning

confidence: 99%

Spur-Free and Stable Digital Delta-Sigma Modulator via Using HK-EFM

Fan

Shi

Liao

et al. 2017

This paper presents a new multi-stage noise-shaping (MASH) digital delta-sigma modulator (DDSM), denoted as HJ-MASH DDSM which can remove spurs in the output spectrum and has long sequence lengths than Jinook structure and HK-MASH in the worst input case by applying HK-EFM in the first stage error feedback modulator (EFM) of the DDSM. In addition, the proposed HJ-MASH DDSM lowers the difficulty of constructing higher order MASH DDSMs compared to HK-MASH DDSM. While the performance and stability are all superior to Jinook structure for all constant inputs, especially for the input which correspond to minimum cycle lengths. The digital delta-sigma modulator applied in fractional-N frequency synthesizers ameliorates the synthesizer's spectral purity apparently by verification.

IEEE Trans. Microwave Theory Techn.

“…Therefore any increase in data rate will also require an increase of the loop bandwidth, which comes at a cost of increased quantization noise (QN) due to the sigma-delta modulator (SDM) appearing at the PLL output [1]. Many techniques have been suggested in the literature to reduce the impact of the SDM QN at the output of the PLL [2], [3]. Even though this reduction of the SDM QN would prima facie appear to help increasing the transmitter (TX) data rate, in reality it solves only a part of the problem.…”

Section: Introductionmentioning

confidence: 99%

Reducing Energy Dissipation in ULP Systems: PLL-Free FBAR-Based Fast Startup Transmitters

Thirunarayanan

Ruffieux

Enz

2015

The energy dissipated by conventional phase-lockedloop-based transmitters (TXs) during the long startup phase is a major bottleneck that reduces the energy autonomy of duty-cycled ultra-low-power systems. In order to tackle this problem, this paper presents a loop-free TX based on a film-bulk acoustic wave resonator (FBAR) that has a 5-s startup time and requires just 3-s for channel switching. The presented TX takes advantage of the high-frequency stability of the FBAR digitally controlled oscillator (DCO) to operate in open loop mode. In order to avoid the problem of the same frequency stability that also hinders addressing multiple channels, the DCO output is mixed with a divided down version (which gives the IF) of itself. By adjusting the division ratio suitably, frequency of the system can then be tuned. To further relax the tuning requirements on the FBAR, the divider for producing the IF is implemented as a phase-switching divider with a step size of 0.2. Integrated in a 65-nm technology node, the TX can address all the bands within the 2.36-2.5-GHz frequency range viz. Medical body area network, industrial, scientific, and medical, and low-power active medical implant bands. Moreover, this TX is able to reach up to 16-Mb/s peak data rate while consuming 9.2 mA at 1.2 V.Index Terms-Film-bulk acoustic wave resonator (FBAR), phase-locked loop (PLL)-free transmitter (TX), phase-switching divider (PSD), quantization noise (QN), ultra-low-power (ULP) systems.