Quantitative model of CMOS inverter chain ring oscillator's effective capacitance and its improvements in 14nm FinFET technology

Mun, Seong Yeol; Cho, J.; Zhu, B.; Agnihotri, Prashant; Wong, Chen-Syuan; Lee, T. J.; Mahajan, Vinayak; Liu, B. W.; Shi, Yong; Wang, Hong; Ciavatti, J.; Lee, J. G.; Samavedam, Srikanth; Sohn, Dong Kyun

doi:10.1109/icmts.2018.8383787

Cited by 3 publications

(1 citation statement)

References 4 publications

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“…5(c). The smaller separation distance leads to reduced device capacitance due to less gate-S/D overlap area [28] and mitigated gate fringing effects [4], which are the largest components of parasitic capacitance in a multi-gate CMOS logic circuit [41]- [43]. It is also observed that as DN/P is reduced, the slope of Ceff decreases as the capacitive coupling between the top and bottom device increases with closer distance.…”

Section: B Ac Electrothermal Characteristics Of Cfet In Cmos Inverter Operationsmentioning

confidence: 99%

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

et al. 2021

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For the first time, the electrothermal characteristics of a three-dimensional (3D) monolithic complementary FET (CFET) in DC operation as well as in AC CMOS operation were investigated with TCAD simulations. The self-heating effect (SHE) in a monolithic CFET is expected to be a critical problem given its highly compact architecture. DC analysis of the individual NFET and PFET devices revealed that increasing the channel width from 5.0 to 7.0 nm improved the thermal resistance up to 8.5% and the RC delay up to 9.6%, while greatly deteriorating the on/off ratio. AC CMOS inverter simulations of the CFET showed that reducing the NFET/PFET vertical separation from 30 to 10 nm resulted in 11.9% faster operation frequency and 3.4% reduced dynamic power loss, but 11.2% higher rise in device temperature. The clear trade-off relationships between the thermal and electrical performance factors necessitate optimization of the device dimension parameters. These findings are expected to provide critical insight for the design technology co-optimization (DTCO) in the 3-nm regime.INDEX TERMS Complementary FET (CFET), self-heating effect (SHE), 3D monolithic integration, TCAD, thermal resistance, time delay, figure of merit (FoM), CMOS inverter, device optimization.

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Section: B Ac Electrothermal Characteristics Of Cfet In Cmos Inverter Operationsmentioning

confidence: 99%

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

et al. 2021

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show abstract

Traveling-Wave Ring Oscillator – Simulations and Prototype Measurements for a New Architecture for a Transmission Line Based Oscillator

Likhterov

Belenky

2018

2018 IEEE International Conference on the Science of Electrical Engineering in Israel (ICSEE)

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A Novel Customized RC Tightened Corner Modeling Methodology Using Statistical SPICE Simulation in Advanced FinFET Technology

Sun¹,

Wong²,

Tseng³

et al. 2018

2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

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Quantitative model of CMOS inverter chain ring oscillator's effective capacitance and its improvements in 14nm FinFET technology

Cited by 3 publications

References 4 publications

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)

Traveling-Wave Ring Oscillator – Simulations and Prototype Measurements for a New Architecture for a Transmission Line Based Oscillator

A Novel Customized RC Tightened Corner Modeling Methodology Using Statistical SPICE Simulation in Advanced FinFET Technology

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