Quantitative and predictive model of reading current variability in deeply scaled vertical poly-Si channel for 3D memories

Toledano-Luque, M.; Degraeve, R.; Kaczer, B.; Tang, Bao-Jun; Roussel, Ph.; Weckx, Pieter; Franco, J.; Arreghini, A.; Suhane, A.; Kar, Gouri Sankar; bosch, G. Van den; Groeseneken, G.; Houdt, J. Van

doi:10.1109/iedm.2012.6479009

Cited by 31 publications

(10 citation statements)

References 6 publications

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“…4(c)) are also observed. The STS distribution in epi-Si devices appears to be bimodal: a tightly distributed mode is centered around 70 mV/dec, similar to in planar epi-Si devices [8], and a more widely distributed mode is observed, with STS-values that stretch up to ~300mV/dec. Epi-Si 0.6 Ge 0.4 performs worse than epi-Si; it shows a better I D than poly-Si, but the highest STS and V th .…”

Section: Introductionmentioning

confidence: 79%

“…The transconductance (g m ) is then extracted from these I D -V G curves in between charging events [8]. As a result, the intrinsic g m value is obtained, and its statistical distribution is shown in Fig.…”

Section: Electrical Characterizationmentioning

confidence: 99%

“…Therefore, poly-Si is the typical channel material. Unfortunately, the conduction in poly-Si is a major concern, since the drive current for the read operation (I D ) is low and unstable, and presents a broad distribution [7,8]. Current is hampered by grain boundaries and Si-SiO 2 interface defects leading to a percolating conduction through the defective material.…”

Section: Introductionmentioning

confidence: 99%

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Integration and Electrical Evaluation of Epitaxially Grown Si and SiGe Channels for Vertical NAND Memory Applications

Capogreco

Degraeve

Lisoni

et al. 2015

2015 IEEE International Memory Workshop (IMW)

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__ Epitaxially grown Si and Si 0.6 Ge 0.4 are integrated as replacement of poly-Si channel in vertical cylindrical transistors for vertical NAND memory application, in order to investigate the impact of the grain boundaries on current conduction. Epi-Si outperforms both poly-Si and Epi-SiGe channels, resulting in the best conduction, with large improvement on both sub-threshold swing and transconductance (g m ). The experimentally observed g m bimodal distribution for epi-Si is corroborated and explained through a resistive network model: lower g m conduction occurs when current needs to cross a high resistance boundary, whereas higher g m is obtained when this boundary is not present.

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Section: Introductionmentioning

confidence: 79%

Section: Electrical Characterizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Integration and Electrical Evaluation of Epitaxially Grown Si and SiGe Channels for Vertical NAND Memory Applications

Capogreco

Degraeve

Lisoni

et al. 2015

2015 IEEE International Memory Workshop (IMW)

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“…RTN improves for larger cells and smaller average grain size, as shown in Figure 40 [326,334] (where it was measured above the threshold). Other works also reported poor reliability and higher variability in 3D NAND for large poly-Si grain size [317,335].…”

Section: Polysilicon Grainsmentioning

confidence: 97%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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“…5b. When the charge center is in a critical current path, a significant glitch, usually characterized as a single-electron V th -shift, ΔV th,1e (2), is observed in the I-V curve. The modeled magnitude of ΔV th,1e is widely distributed and can be as large as several tens of mV, in agreement with experimental data as demonstrated in fig.…”

Section: Model For V G >V Thmentioning

confidence: 99%

Characterizing grain size and defect energy distribution in vertical SONOS poly-Si channels by means of a resistive network model

Degraeve

Toledano-Luque

Arreghini

et al. 2013

2013 IEEE International Electron Devices Meeting

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The characterization of vertical poly-Si transistors, important for optimizing vertical SONOS memory configurations, is studied by means of a resistive network model. The statistical variation of the I SD -V G characteristics allows to extract the poly-Si grain size and from the sub-threshold regime information on the energy distribution of the poly-Si defects is extracted. This model indicates the separated impact of interface states and poly-Si states on current and V th . Introduction and purpose

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Quantitative and predictive model of reading current variability in deeply scaled vertical poly-Si channel for 3D memories

Cited by 31 publications

References 6 publications

Integration and Electrical Evaluation of Epitaxially Grown Si and SiGe Channels for Vertical NAND Memory Applications

Integration and Electrical Evaluation of Epitaxially Grown Si and SiGe Channels for Vertical NAND Memory Applications

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Characterizing grain size and defect energy distribution in vertical SONOS poly-Si channels by means of a resistive network model

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