Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors

Shrivastava, Aviral; Rhisheekesan, Abhishek; Jeyapaul, Reiley; Wu, Carole-Jean

doi:10.1145/2593069.2593195

Cited by 26 publications

(8 citation statements)

References 17 publications

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“…It means that sometimes is better not protect the application instead of protecting using only a control-flow technique. This result corroborates [24], in which the authors stated that control-flow techniques make the processor more vulnerable to soft errors because they do not provide enough fault coverage to compensate the extra execution time. However, this statement cannot be taken as a rule since the reliability also depends on the target application and processor, as showed by the greater MWTF presented by SETA in 2 out of 3 cases.…”

Section: Mwtf = Amount Of Work Completed Number Of Errors Encounteredsupporting

confidence: 87%

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

Chielle

Rosa

Rodrigues

et al. 2016

IEEE Trans. Nucl. Sci.

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ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.

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Section: Mwtf = Amount Of Work Completed Number Of Errors Encounteredsupporting

confidence: 87%

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

Chielle

Rosa

Rodrigues

et al. 2016

IEEE Trans. Nucl. Sci.

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“…A signature is a binary vector of the form S = (X = (x 1 , x 2 ), f(Y, X)) where x 1 , x 2 and f are 10 bit vectors that represent elements from the finite field F 2 10 . The value of f for k = k max is computed as follows f (Y, X) = y 1 X (0,1) + y 2 X (0,2) + ...y 49 X (0,49) + y 50 X (1,0) + y 51 X (1,1) + ...y 98 X (1,48) + . .…”

Section: Constructionmentioning

confidence: 99%

“…CFC has been proposed to cope with reliability issues for both transient and permanent faults ( [1], [2]) and more recently, with security issues caused by the injection of malicious faults [3], [4], which can allow an attacker to either bypass security checks or retrieve secret information. Software based CFC solutions which modify the code rely on the assumption that the code stored in memory is not being maliciously tampered with and thus cannot provide security [5]; on the other hand, hardware-based CFC solutions, such as [6] can detect malicious code and data tampering at run-time.…”

Section: Introductionmentioning

confidence: 99%

Nonlinear Codes for Control Flow Checking

Natale

Keren

2020

2020 IEEE European Test Symposium (ETS)

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“…The issue of unprotected code is unresolved as all these methods require control transfer information for dynamic shared libraries, which is unknown at compile time. Their fault model is restricted to a limited area of processor like the program counter (PC), parts of few pipeline registers, link registers and so on [27] and thus has poor fault coverage.…”

Section: Related Workmentioning

confidence: 99%

Soft‐error reliable architecture for future microprocessors

Gopalakrishnan

Singh

2019

IET Computers & Digital Techniques

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The transient error is the failure of the device due to transient hardware faults caused by high-energy particles like neutron and alpha particle strikes. In this study, the authors propose two schemes of fault-tolerant architecture. The first scheme is a hardware-based solution called REMO that combines the best features of space and time redundancy. REMO provides very high fault coverage with minimum overheads in performance, power and area. The second scheme, REMORA combines the best features of hardware and software approaches of fault tolerance. The persistent issue of unprotected code which exists in software approaches is eliminated in this proposal. Simulation results from a SPEC2006 benchmark suite indicate, REMO incurs an increase in the area of about 6%, power overhead is 9% in spite of redundant execution and a negligible performance penalty during a fault-free run. In REMORA, performance degradation increases to 12%. The code size inflation is close to 12%. This is due to the additional signature instructions inserted into the application program. In this study, the authors have explored the possibility of eliminating this penalty by embedding the signatures in control flow instructions. The power and area overhead of REMORA is on par with REMO.

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Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors

Cited by 26 publications

References 17 publications

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

Nonlinear Codes for Control Flow Checking

Soft‐error reliable architecture for future microprocessors

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