Quantile – Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing

Farayola, Praise O.; Chaganti, Shravan K.; Obaidi, Abdullah O.; Sheikh, Abalhassan; Ravi, S.; Chen, Degang

doi:10.1109/vts48691.2020.9107616

Cited by 17 publications

(3 citation statements)

References 21 publications

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“…Most of these methods assume that the device characteristics on the wafer gradually change with wafer coordinates; however, this assumption does not hold for the measurement of radio frequency (RF) circuits under multi-site testing [18]- [20], in which a probe card is adapted to simultaneously probe multiple devices under test (DUTs). The contact of the probe card with the DUTs to be tested is named the touchdown and, the position of the needles in a touchdown is called a site.…”

Section: Introductionmentioning

confidence: 99%

Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing

MIAN,

NAKAMURA,

KAJIYAMA

et al. 2024

IEICE Trans. Fundamentals

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Wafer-level performance prediction techniques have been increasingly gaining attention in production LSI testing due to their ability to reduce measurement costs without compromising test quality. Despite the availability of several efficient methods, the site-to-site variation commonly observed in multi-site testing for radio frequency circuits remains inadequately addressed. In this manuscript, we propose a wafer-level performance prediction approach for multi-site testing that takes into account the site-to-site variation. Our proposed method is built on the Gaussian process, a widely utilized wafer-level spatial correlation modeling technique, and enhances prediction accuracy by extending hierarchical modeling to leverage the test site information test engineers provide. Additionally, we propose a test-site sampling method that maximizes cost reduction while maintaining sufficient estimation accuracy. Our experimental results, which employ industrial production test data, demonstrate that our proposed method can decrease the estimation error to 1/19 of that a conventional method achieves. Furthermore, our sampling method can reduce the required measurements by 97% while ensuring satisfactory estimation accuracy.

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Section: Introductionmentioning

confidence: 99%

Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing

MIAN,

NAKAMURA,

KAJIYAMA

et al. 2024

IEICE Trans. Fundamentals

View full text Add to dashboard Cite

show abstract

“…[11,12] also proposes methods to group/cluster defects in an analog circuit and consequently reduce number of test simulations and test time. Others also utilizes the multi-site testing capabilities of modern automated test equipment (ATE) to reduce test time [3,[13][14]. More recently, several design for test and build in self-test methods [15][16][17][18] have all been proposed as strategies to ensure continued reliability of IC through online health monitoring.…”

Section: Introductionmentioning

confidence: 99%

Defect Detection and Localization in Operational Amplifiers using Digital Control and Monitor Circuits

Sekyere,

Marampally,

Chen

2023

Preprint

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Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial building blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage as well as performing diagnosis and defect localization in these circuits has been proven to be a difficult/expensive task even with sophisticated analog and digital testing circuitry. ISO26262 Standard for functional safety (FuSa) places stringent requirement that an automotive IC must have a very high defect coverage (usually greater than 90%). This reinforce the need to improve the robustness in the design of analog and mixed signal (AMS) circuits to ensure their reliability especially if they are used in mission critical industries. This paper presents a simple defect detection, diagnosis, and localization method for op amps including Widlar current reference and biasing circuitry and can be used both for production and in-field tests for online health monitoring to ensure continued reliability during integrated circuits’ (IC) lifetime. We rigorously validate all our results using extensive transistor-level simulations of two op amps architectures (folded cascode and telescopic) designed in MUSE TSMC 180nm technology. For the folded cascode op amp, the proposed method achieves a worst-case defect coverage of 94.5% and a best-case coverage of 98%. Similarly for the telescopic op amp, the proposed method attains a worst- and best-case defect coverage of 97% and 99% respectively. Furthermore, in this work, we also propose a defect diagnosis and localization strategy using recorded bit streams from states of digital injectors and detectors.

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“…Most of these methods assume that the device characteristics on the wafer gradually change with wafer coordinates; however, this assumption does not hold for the measurement of radio frequency (RF) circuits under multi-site testing [20]- [22], in which a probe card is adapted to simultaneously probe multiple devices under test (DUTs). The contact of the probe card with the DUTs to be tested is called a touchdown.…”

Section: Introductionmentioning

confidence: 99%

Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process

Shintani¹,

Mian²,

Nakamura³

et al. 2021

Preprint

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Wafer-level performance prediction has been attracting attention to reduce measurement costs without compromising test quality in production tests. Although several efficient methods have been proposed, the site-to-site variation, which is often observed in multi-site testing for radio frequency circuits, has not yet been sufficiently addressed. In this paper, we propose a wafer-level performance prediction method for multi-site testing that can consider the site-to-site variation. The proposed method is based on the Gaussian process, which is widely used for waferlevel spatial correlation modeling, improving the prediction accuracy by extending hierarchical modeling to exploit the test site information provided by test engineers. In addition, we propose an active test-site sampling method to maximize measurement cost reduction. Through experiments using industrial production test data, we demonstrate that the proposed method can reduce the estimation error to 1/19 of that obtained using a conventional method. Moreover, we demonstrate that the proposed sampling method can reduce the number of the measurements by 97% while achieving sufficient estimation accuracy.

show abstract

Quantile – Quantile Fitting Approach to Detect Site to Site Variations in Massive Multi-site Testing

Cited by 17 publications

References 21 publications

Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing

Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing

Defect Detection and Localization in Operational Amplifiers using Digital Control and Monitor Circuits

Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process

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