Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device

Abstract

Many of the pins on a modern chip are used for power delivery. If fewer pins were used to supply the same current, the wires and pins used for power delivery would have to carry larger currents over longer distances. This results in an "IR-drop" problem, where some of the voltage is dropped across the long resistive wires making up the power delivery network, and the eventual circuits experience fluctuations in their supplied voltage. The same problem also manifests if the pin count is the same, but the current draw is higher. IR-drop can be especially problematic in 3D DRAM devices because (i) low cost (few pins and TSVs) is a high priority, (ii) 3D-stacking increases current draw within the package without providing proportionate room for more pins, and (iii) TSVs add to the resistance of the power delivery network.This paper is the first to characterize the relationship between the power delivery network and the maximum supported activity in a 3D-stacked DRAM memory device. The design of the power delivery network determines if some banks can handle less activity than others. It also determines the combinations of bank activities that are permissible. Both of these attributes can feed into architectural policies. For example, if some banks can handle more activities than others, the architecture benefits by placing data from high-priority threads or data from frequently accessed pages into those banks. The memory controller can also derive higher performance if it schedules requests to specific combinations of banks that do not violate the IR-drop constraint.We first define an IR-drop-aware scheduler that encodes a number of activity constraints. This scheduler, however, falls short of the performance of an unrealistic ideal PDN

Improving DRAM performance by parallelizing refreshes with accesses

“…Instead, refresh operations are staggered (pipelined) across banks [31]. The main reason is that refreshing every bank simultaneously would draw more current than what the power delivery network can sustain, leading to potentially incorrect DRAM operation [31,38]. Because a REF ab command triggers refreshes on all the banks within a rank, the rank cannot process any memory requests during tRFC ab , The length of tRFC ab is a function of the number of rows to be refreshed.…”

“…Power Integrity. Because an ACTIVATE draws a lot of current, DRAM standards define two timing parameters to constrain the activity rate of DRAM so that ACTIVATEs do not over-stress the power delivery network [11,38]. The first parameter is the row-to-row activation delay (tRRD) that specifies the minimum waiting time between two subsequent ACTIVATE commands within a DRAM device.…”

A scalable processing-in-memory accelerator for parallel graph processing

“…Although the increased power consumption may have a negative impact on device temperature, the power consumption is expected to be still within the power budget according to a recent industrial research on thermal feasibility of 3D-stacked PIM [9]. Specifically, assuming that a logic die of the HMC has the same area as an 8 Gb DRAM die (e.g., 226 mm 2 [54]), the highest power density of the logic die across all workloads in our experiments is 94 mW/mm 2 in Tesseract, which remains below the maximum power density that does not require faster DRAM refresh using a passive heat sink (i.e., 133 mW/mm 2 [9]). …”

Making the Case for Feature-Rich Memory Systems: The March Toward Specialized Systems

“…Because of process variation, some regions of a die may be faster than others, and some regions may be more error prone than others. Similarly, operations that consume large amounts of current (e.g., writes in NVMs) will introduce static or dynamic IR-drop and pose severe worst-case constraints on DRAM timing parameters [38].…”