A scalable processing-in-memory accelerator for parallel graph processing

Ahn, Junwhan; Hong, Ser Gi; Yoo, Sungjoo; Mutlu, Onur; Choi, Ki‐Young

doi:10.1145/2749469.2750386

Cited by 583 publications

(443 citation statements)

References 62 publications

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“…al. have proposed the Tesseract architecture, where programmable graph accelerators are integrated into a 3D memory [43].…”

Section: Google's Tensor Processing Unitmentioning

confidence: 99%

Emerging Accelerator Platforms for Data Centers

Özdal

2018

IEEE Des. Test

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Today's server architectures are designed considering the needs of a wide range of applications. For example, superscalar processors include complex control logic for out of order execution to extract instruction-level parallelism (ILP) from arbitrary programs. However, not all workloads utilize the features of a superscalar processor effectively. For example, a workload that exhibits a regular execution pattern (e.g. a dense linear algebra kernel) may not require the expensive ILP control logic for parallelism. Instead, it can be run on a throughput-oriented architecture with thousands of simple cores, such as a GPU, which can lead to much better performance and power efficiency. On the other hand, only a limited class of data-parallel applications can utilize the high throughputs provided by such architectures. As a matter of fact, existing CPU and GPU platforms may not be the most efficient choices for the compute patterns of a wide range of applications.For big data workloads, access to data is typically at least as important bottleneck as computation. The memory subsystems of today's CPU architectures are optimized for workloads that have reasonable data access locality. CPU cache hierarchies include different sizes of caches, which help capture different levels of access localities in different applications. However, if an application exhibits very little or no locality, the data access operations become inefficient for these architectures.As an example, let us consider graph applications that run on very large and unstructured datasets. Typically, the data of a vertex is computed/updated based on the data of its neighbors. In an unstructured graph, the neighbors of a vertex are stored in memory locations that may be far from each other. So, traversing the neighbors of a vertex may involve a random memory access per neighbor. If the graph is large enough so that it does not fit into the last level cache (LLC), each access to a neighbor's data may require a random DRAM access, which is typically hundreds of clock cycles. However, existing CPU architectures are not optimized for frequent random DRAM accesses. For example, each Intel Haswell Xeon core has 10 line-fill-buffers (LFBs), which means that each core can handle at most 10 L1 cache misses at a given time. However, an off-chip DRAM latency of hundreds of cycles requires hundreds of outstanding memory requests to be able to utilize the full DRAM bandwidth available in the system [1]. It was reported that 10 or more Xeon cores were needed for various graph applications to fully utilize the available DRAM bandwidth [2]. Furthermore, due to the low compute to memory-access ratios in graph applications, these cores are frequently stalled while waiting for data from off-chip memory. This leads to high power consumption by 10+ superscalar cores while not doing useful work. It was shown that custom architectures that target such communication patterns have the potential to improve power efficiency by a factor of 50x or more compared to the general-purpose CPU...

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“…al. have proposed the Tesseract architecture, where programmable graph accelerators are integrated into a 3D memory [43].…”

Section: Google's Tensor Processing Unitmentioning

confidence: 99%

Emerging Accelerator Platforms for Data Centers

Özdal

2018

IEEE Des. Test

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“…Some new DRAM architectures [2,11,16] contain a logic layer. Many techniques (e.g., [4,5,8,9,24]) have been proposed to exploit the logic layer to implement some computation close to DRAM. However, these architectures still have limited memory bandwidth available to the logic layer, and our mechanism can provide much higher throughput and efficiency for bitwise AND/OR operations.…”

Section: Related Workmentioning

confidence: 99%

Fast Bulk Bitwise AND and OR in DRAM

Seshadri

Hsieh

Boroumand

et al. 2015

IEEE Comput. Arch. Lett.

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179

133

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Abstract-Bitwise operations are an important component of modern day programming, and are used in a variety of applications such as databases. In this work, we propose a new and simple mechanism to implement bulk bitwise AND and OR operations in DRAM, which is faster and more efficient than existing mechanisms. Our mechanism exploits existing DRAM operation to perform a bitwise AND/OR of two DRAM rows completely within DRAM. The key idea is to simultaneously connect three cells to a bitline before the sense-amplification. By controlling the value of one of the cells, the sense amplifier forces the bitline to the bitwise AND or bitwise OR of the values of the other two cells. Our approach can improve the throughput of bulk bitwise AND/OR operations by 9.7X and reduce their energy consumption by 50.5X. Since our approach exploits existing DRAM operation as much as possible, it requires negligible changes to DRAM logic. We evaluate our approach using a real-world implementation of a bit-vector based index for databases. Our mechanism improves the performance of commonly-used range queries by 30% on average.

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“…Citing severe bandwidth limitations in conventional computer architecture as datasets continue to grow, Ahn et al [1] introduced Tesseract, a 3D Processing-in-Memory accelerator for large-scale graph processing. In another work, Ahn et al [2] developed a hybrid-memory-cube based framework that automatically decides whether to execute PIM operations in memory or processors depending on the locality of data.…”

Section: D Processing-in-memory Architecturesmentioning

confidence: 99%

“…E and F are partial score results of the affine gap model [22]. AD[0], AD [1] and AD [2] contain scoring matrix anti-diagonals. Scores are represented by 32-bit integers.…”

Section: System Architecturementioning

confidence: 99%

From Processing-in-Memory to Processing-in-Storage

Kaplan

Yavits

Ginosar

2017

JSFI

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Near-data in-memory processing research has been gaining momentum in recent years. Typical processing-in-memory architecture places a single or several processing elements next to a volatile memory, enabling processing without transferring data to the host CPU. The increased bandwidth to and from volatile memory leads to performance gain. However processing-in-memory does not alleviate von Neumann bottleneck for big data problems, where datasets are too large to fit in main memory.We present a novel processing-in-storage system based on Resistive Content Addressable Memory (ReCAM). It functions simultaneously as a mass storage and as a massively parallel associative processor. ReCAM processing-in-storage resolves the bandwidth wall by keeping computation inside the storage arrays, without transferring it up the memory hierarchy.We show that ReCAM based processing-in-storage architecture may outperform existing processing-in-memory and accelerator based designs. ReCAM processing-in-storage implementation of Smith-Waterman DNA sequence alignment reaches a speedup of almost five over a GPU cluster. An implementation of in-storage inline data deduplication is presented and shown to achieve orders of magnitude higher throughput than traditional CPU and DRAM based systems.Keywords IntroductionUntil the breakdown of Dennard scaling designers focused on improving performance of a single core by increasing instruction level parallelism. In recent years, as Dennard scaling slowed down but Moore's law endured, the focus has shifted to improving parallelism by increasing the number of cores in multicore processors [16]. However, memory bandwidth does not improve at the same rate, making von Neumann bottleneck one of the main performance limiting factors.Data is typically fetched to CPU's main memory from a non-volatile storage such as hard disks or Flash SSDs. Consequently, storage bandwidth and access time pose a major constraint to performance improvement. The problem worsens in datacenter cloud environment, where datasets are distributed among multiple nodes across the datacenter. In such case, data transfer adds latency and reduces bandwidth even further, lowering the performance upper bound.This challenge has motivated renewed interest in Near-Data Processing (NDP) [7]. The main premise of NDP is shifting computing closer to data. NDP seeks to minimize data movement by computing at the most appropriate location in the memory hierarchy, which can be cache, main memory or persistent storage. With NDP, less data needs to be transferred through levels of hierarchy, thus alleviating the limited bandwidth problem. Placing computing resources at the cache level or in main memory (also known as Processing-in-Memory or PiM) does not address the emerging big data problems, where datasets are too large to fit in main memory.Resistive CAM (ReCAM), a storage device based on emerging resistive materials in the bitcell with a novel non-von Neumann Processing-in-Storage (PRinS) compute paradigm, is proposed in order to mitigate the s...

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A scalable processing-in-memory accelerator for parallel graph processing

Cited by 583 publications

References 62 publications

Emerging Accelerator Platforms for Data Centers

Emerging Accelerator Platforms for Data Centers

Fast Bulk Bitwise AND and OR in DRAM

From Processing-in-Memory to Processing-in-Storage

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