2017
DOI: 10.1109/tc.2016.2640296
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Quality Configurable Approximate DRAM

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Cited by 65 publications
(53 citation statements)
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“…In the hypothesis of a circuit consisting of true-cells, different error rates and looseness levels are explored. For example, an error rate of about 10 −3 is obtained in case of a 60x increase in refresh period [5]. The figure also shows that the looseness level can be used in order to rise SNR orthogonally to error rate, at the cost of keeping some bits exact.…”
Section: Resultsmentioning
confidence: 91%
See 2 more Smart Citations
“…In the hypothesis of a circuit consisting of true-cells, different error rates and looseness levels are explored. For example, an error rate of about 10 −3 is obtained in case of a 60x increase in refresh period [5]. The figure also shows that the looseness level can be used in order to rise SNR orthogonally to error rate, at the cost of keeping some bits exact.…”
Section: Resultsmentioning
confidence: 91%
“…These error models take into account the techniques proposed and the circuital implementations for approximate DRAM and SRAM. Reducing refresh rate in DRAMs and allowing errors is a strategy for reducing power consumption that has produced many research works in the field of approximate memories [1], [5], [10]. The effects of these techniques at bit level can vary depending on DRAM architectures and will be discussed in Section III-A.…”
Section: Memoriesmentioning
confidence: 99%
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“…As regards DRAMs, different techniques to reduce refresh rate have been proposed. 1,[8][9][10][11] In fact, in exact DRAMs refresh time interval is set according to the worst case access-statistics of the most leaky cells. Commercial DRAM modules, for example, have a worst case retention time of 64 ms determined by the leakiest cells in the entire array.…”
Section: Related Work and Contributionmentioning
confidence: 99%
“…In Ref. [10], after an experimental characterization of memory errors as a function of the DRAM refresh-rate, the authors propose a methodology for constructing a quality configurable approximate DRAM system. Experiments were performed on a FPGA board where a soft-processor (Nios II) and a DDR3 memory controller (UniPHY) are programmed; they revealed a reduction in DRAM refresh power of up to 73% on average.…”
Section: Related Work and Contributionmentioning
confidence: 99%