Quality assurance in memory built-in self-test tools

Au, Albert; Pogiel, Artur; Rajski, J.; Sydow, Piotr; Tyszer, Jerzy; Zawada, Justyna

doi:10.1109/ddecs.2014.6868760

Cited by 5 publications

(3 citation statements)

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“…The cache is modeled in CACTI [36] with 128 Byte set size and two different block sizes, and the impact of process variation is modeled using the threshold voltage variation model given in Eq. (5). As shown in the figure, the smaller block size (Fig.…”

Section: Motivation and Ideamentioning

confidence: 90%

“…Built-In Self-Test (BIST) is a widely used technique to test VLSI system on chip [22]. Since memory components occupy majority of the chip area, BIST plays a significant role in testing large and complex memory arrays easily [5,22]. In order to determine the runtime supply voltage downscaling potential of caches, it is essential to assume a cache memory is equipped with BIST infrastructure to test the entire memory.…”

Section: Built-in Self-test (Bist) Based Runtime Operating Voltage Admentioning

confidence: 99%

“…In a conventional BIST, the BIST controller generates the test addresses and test patterns (finite number of read/write operations). Then, the test is performed, and the test result is compared with the expected response to determine the failing cells [5]. In this case, however, since the BIST module has to determine the minimum scalable voltage of each block, the test controller has to be modified in order to iteratively test and generate the minimum scalable voltages of each block.…”

Section: Built-in Self-test (Bist) Based Runtime Operating Voltage Admentioning

confidence: 99%

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Reliability Analysis and Mitigation of Near-Threshold Voltage (NTC) Caches

Gebregiorgis

Bishnoi

Tahoori

2020

Dependable Embedded Systems

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Near-threshold computing (NTC) has significant role in reducing the energy consumption of modern very large-scale integrated circuits designs. However, NTC designs suffer from functional failures and performance loss. Understanding the characteristics of the functional failures and variability effects is of decisive importance in order to mitigate them, and get the utmost NTC benefits. This chapter presents a comprehensive cross-layer reliability analysis framework to assess the effect of soft error, aging, and process variation in the operation of near-threshold voltage caches. The objective is to quantify the reliability of different SRAM designs, evaluate voltage scaling potential of caches, and to find a reliability-performance optimal cache organization for an NTC microprocessor. In this chapter, the soft error rate (SER) and static noise margin (SNM) of 6T and 8T SRAM cells and their dependencies on aging and process variation are investigated by considering device, circuit, and architecture-level analysis.

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Section: Motivation and Ideamentioning

confidence: 90%

Section: Built-in Self-test (Bist) Based Runtime Operating Voltage Admentioning

confidence: 99%

Section: Built-in Self-test (Bist) Based Runtime Operating Voltage Admentioning

confidence: 99%

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