The detection accuracy of a conventional phase-locked loop for a single phase is affected by the interference of the DC component and harmonic component when the grid has a lot of problems such as harmonic interference and DC offset, and It will be unable to accurately track the grid voltage frequency and phase. The traditional APF-PLL is improved to address this problem. An improved phase-locking algorithm is proposed, combining a CSOGI and a FLL with the conventional single-phase phase-locked loop. The method incorporates CSOGI into the APF-PLL pre-stage to reduce interference from DC and harmonic components, while FLL achieves the frequency tracking of the input signal and improves the adaptivity and dynamic response speed of the phase-locked loop. Through simulation verification, the proposed new phase-locked loop can improve the frequency tracking capability, dynamic performance, and precision of the locking phase of the PLL.