Quad Precision Floating Point on the IBM z13

Lichtenau, Cedric; Carlough, S.R.; Mueller, Silvia Melitta

doi:10.1109/arith.2016.26

Cited by 18 publications

(11 citation statements)

References 12 publications

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“…Table 6 compares the latency and total time of the proposed division unit with these of classic processors for FP SP and DP with normalized operands and result, Intel Penryn [59], IBM zSeries [60], IBM z13 [61], HAL Sparc [62], AMD K7 [63], AMD Jaguar [64].…”

Section: Related Work and Comparisonsmentioning

confidence: 99%

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Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Xia

Liu

et al. 2021

Applied Sciences

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Floating-point division is indispensable and becoming increasingly important in many modern applications. To improve speed performance of floating-point division in actual microprocessors, this paper proposes a low-latency architecture with a multi-precision architecture for floating-point division which will meet the IEEE-754 standard. There are three parts in the floating-point division design: pre-configuration, mantissa division, and quotient normalization. In the part of mantissa division, based on the fast division algorithm, a Predict–Correct algorithm is employed which brings about more partial quotient bits per cycle without consuming too much circuit area. Detailed analysis is presented to support the guaranteed accuracy per cycle with no restriction to specific parameters. In the synthesis using TSMC, 90 nm standard cell library, the results show that the proposed architecture has ≈63.6% latency, ≈30.23% total time (latency × period), ≈31.8% total energy (power × latency × period), and ≈44.6% efficient average energy (power × latency × period/efficient length) overhead over the latest floating-point division structure. In terms of latency, the proposed division architecture is much faster than several classic processors.

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Section: Related Work and Comparisonsmentioning

confidence: 99%

“…Consequently, the latency is almost halved with respect to that of the radix-4 unit. The IBM z13 processor [61] has a divide unit supporting SP, DP, QP, and all the hexadecimal FP data types. The underlying algorithm is a radix-8 division generating 3 bits per cycle.…”

Section: Related Work and Comparisonsmentioning

confidence: 99%

Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Xia

Liu

et al. 2021

Applied Sciences

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“…Half precision was defined for storage only, but several manufacturers now support it for computation. Quadruple precision is available only in software, with the exception of the IBM z13 mainframe systems, designed for business analytics workloads [8]. Another form of half precision called bfloat16 was introduced by Google on its Tensor Processing Unit and will be supported by Intel in its forthcoming Nervana Neural Network Processor and Cooper Lake processor and on the Armv8-A architecture [9], [10], [11], [12], [13].…”

Section: Mixed Precision Algorithmsmentioning

confidence: 99%

Numerical algorithms for high-performance computational science

Dongarra

Grigori

Higham

2020

Phil. Trans. R. Soc. A.

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A number of features of today’s high-performance computers make it challenging to exploit these machines fully for computational science. These include increasing core counts but stagnant clock frequencies; the high cost of data movement; use of accelerators (GPUs, FPGAs, coprocessors), making architectures increasingly heterogeneous; and multi- ple precisions of floating-point arithmetic, including half-precision. Moreover, as well as maximizing speed and accuracy, minimizing energy consumption is an important criterion. New generations of algorithms are needed to tackle these challenges. We discuss some approaches that we can take to develop numerical algorithms for high-performance computational science, with a view to exploiting the next generation of supercomputers. This article is part of a discussion meeting issue ‘Numerical algorithms for high-performance computational science’.

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“…In each iteration cycle, the partial square-root digits with fixed bit-width can be obtained. At present, the most widely used digital recursive algorithm is SRT, in Intel or IBM [7,8] processor cores, the SRT algorithm with lower radix is used to implemented square-root circuit. In the standard SRT algorithm, although the higher radix can improve the computational performance, the area cost of the lookup table increases in quadratic with the radix [9].…”

Section: Introductionmentioning

confidence: 99%

A Low-Cost High Radix Floating-Point Square-Root Circuit

2021

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In this paper, we propose an efficient architecture of floating-point square-root circuit with low area cost, which is in accordance with the IEEE-754 standard. We extend the principle of the standard SRT algorithm so that the latency and area cost of the proposed circuit are linear with the radix. In addition, no extra computation cycles are required. With 65 nm technology, the area cost of the single-precision floating-point square-root circuit based on proposed architecture is only 6450.84 μm2, and the dynamic power consumption is only 0.764 mW at 300 MHz. The implementation results show that the proposed square-root circuit can reduce the area cost by 60%~90% compared with other designs in the literature.

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Quad Precision Floating Point on the IBM z13

Cited by 18 publications

References 12 publications

Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Numerical algorithms for high-performance computational science

A Low-Cost High Radix Floating-Point Square-Root Circuit

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