PVT variation impact on voltage island formation in MPSoC design

Majzoub, Sohaib; Saleh, R.; Ward, Rabab

doi:10.1109/isqed.2009.4810397

Cited by 8 publications

(18 citation statements)

References 13 publications

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“…Regions of the chip that are timing critical can be mapped to voltage islands powered by relatively high voltages, while regions of the chip that are not timing critical can be mapped to voltage islands powered by relatively low voltages. The regions powered by high voltages consume more power but run faster; the regions powered by low voltages consume less dynamic and static power, but run slower [2][3] [4][5] [6]. In a manycore chip, each voltage island will typically contain many adjacent cores.…”

Section: Introductionmentioning

confidence: 99%

“…Typically, these voltage islands are rectangular [2][4] [5]. In this paper, we show that this is a particularly bad choice in the presence of Process, Voltage, and Temperature variations for manycore architectures.…”

Section: Introductionmentioning

confidence: 99%

“…Process variation can be die-to-die (D2D) or within-die (WID). We focus on WID variation in this work [2][5] [7].…”

Section: Introductionmentioning

confidence: 99%

“…However, if a chip is designed using voltage islands, increasing the voltage of a single core requires increasing the voltage (and hence power) of all cores within the island. Thus, the voltage level for each island is dictated by the slowest core in that island [2][4] [5].…”

Section: Introductionmentioning

confidence: 99%

“…PVT-VARIATION MODELS Before describing our voltage island technique, we review the PVT models assumed in this work. To capture the WID process variation for circuit parameters, such as V t and L eff , we used the methodology described in [2] [7]. The systematic process variation is created using a multivariate normal distribution with a spherical spatial correlation structure.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms

Majzoub

Saleh

Wilton

et al. 2009

2009 International Symposium on System-on-Chip

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Abstract-In this paper, we propose a novel approach to voltage island formation and core placement for energy optimization in manycore architectures under parameter variations at pre-fabrication stage. We group the cores into irregular "cloud-shaped" voltage islands. The islands are created by balancing the desire to limit the spatial extent of each island, to reduce PVT impact, with the communication patterns between islands. Compared to using rectangular islands, our approach leads to power improvements between 10 and 12%.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…Process variation can be die-to-die (D2D) or within-die (WID). We focus on WID variation in this work [2][5] [7].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms

Majzoub

Saleh

Wilton

et al. 2009

2009 International Symposium on System-on-Chip

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Reducing random-dopant fluctuation impact using footer transistors in many-core systems

Majzoub

2015

Integration

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Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning

et al. 2022

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Design-space exploration for low-power manycore design is a daunting and time-consuming task which requires some complex tools and frameworks to achieve. In the presence of process variation, the problem becomes even more challenging, especially the time associated with trial-and-error selection of the proper options in the tools to obtain the optimal power dissipation. The key contribution of this work is the novel use of machine learning to speed up the design process by embedding the tool expertise needed for low power design-space exploration for manycores into a trained neural network. To enable this, we first generate a large volume of data for 36000 benchmark applications by running them under all possible configurations to find the optimal one in terms of power. This is done using our own tool called LVSiM, a holistic manycore optimization program including process variations. A neural network is trained with this information to build in the expertise. A second contribution of this work is to define a new set of features, relevant to power and performance optimization, when training the neural network. At design time, the trained neural network is used to select the proper options on behalf of the user based on the features of any new application. However, one problem encountered with this approach is that the database constructed for machine learning has many outliers due to randomness associated with process variation which creates a major headache for classification -the supervised learning task performed by neural networks. The third key contribution of this work is a novel data coercion algorithm used as a corrective measure to handle the outliers. The proposed data coercion scheme produces results that are within 3.9% of the optimal power consumption compared to 7% without data coercion. Furthermore, the proposed method is about an order of magnitude faster than a heuristic approach and two orders of magnitude faster than a brute-force approach for designspace exploration.

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PVT variation impact on voltage island formation in MPSoC design

Cited by 8 publications

References 13 publications

Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms

Simultaneous PVT-tolerant voltage-island formation and core placement for thousand-core platforms

Reducing random-dopant fluctuation impact using footer transistors in many-core systems

Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning

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