Putting together What Fits together - GrÆStl

Pelnar, Markus; Muehlberghuber, Michael; Hutter, Michael

doi:10.1007/978-3-642-37288-9_12

Cited by 2 publications

(2 citation statements)

References 17 publications

(27 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is evident from the comparison table that our Base Module provides a balance solution such as utilized optimal number of area resources and offered highest throughput. Although area resources of our proposed Base Module is greater than these low-area designs [30]- [32], but enables much higher throughput figures. It is a known fact that area of design can be reduced by folding techniques at the cost of high latency that eventually degrades the performance.…”

Section: B Comparison With Resource-shared Implementationsmentioning

confidence: 99%

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3

Kundi

Khalid

Aziz

et al. 2020

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Cryptographic co-processors are integral to the modern System-on-Chips. Flexibility in such designs serves dual purpose, i.e., it enables acceleration of different essential cryptographic primitives (Encryption/Authentication/Pseudo Random Number Generation (PRNG) ) and also results in design compaction via resource sharing. In this context, a novel resource-shared crypto-coprocessor, named AE$HA-3 is presented, which combines two National Institute of Standards and Technology (NIST) standardized algorithms, i.e., Advance Encryption Standard (AES) and Secure Hash Algorithm-3 (SHA-3). Due to algorithmic dissimilarities, so far no resource-shared implementation enabling AES key scheduling/ enc/dec and SHA-3 has been presented. AE$HA-3 exploits resource-sharing for area reduction, i.e., integration of Look-Up-Tables (I-Tables) for AES enc/dec; logical optimization of Six Input Equation (SixIE) for SHA-3; a Unified XOR Section to carry out both key whitening in AES and SHA-3 transformations. Furthermore, the AES key scheduling was performed using the same resource-shared hardware. The proposed AE$HA-3 on Xilinx Virtex FPGA family results in highest hardware efficiency in terms of Throughput per Slice (TPS), along with a 49.37% area consumption reduction, when compared against the smallest stand-alone implementations presented to date.

show abstract

Section: B Comparison With Resource-shared Implementationsmentioning

confidence: 99%

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3

Kundi

Khalid

Aziz

et al. 2020

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…However, Fugue was a secondround candidate that got eliminated due to security flaws and its average throughput-to-area ratio [7]. Other studies [8][9][10][11] have implemented resource-shared AES with Grøstl-256 on different FPGA platforms. Compared to Keccak, Grøstl-256 has relatively small security margins, lower throughput, throughput/area, and energy consumption-per-bit on FPGAs and ASICs [12].…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of a flexible Multi-purpose Cryptographic System on low cost FPGA

Maache

Kalache

2023

Int. j. electr. comput. eng. syst. (Online)

View full text Add to dashboard Cite

The design of cryptographic hardware that supports multiple cryptographic primitives is common in literature. In this work, a new design is presented consisting of a multi-purpose cryptographic system featuring both 128-bit pipelined AES-CORE (Advanced Encryption Standard) for high-speed symmetric encryption and a Keccak hash core on a low-cost FPGA. The KECCAK-CORE’s security and performance parameters are tunable in the sense that capacity, bitrate, and the number of rounds can be user-defined. Such flexibility enables the core to suit a large range of security requirements. The structure of Keccak’s sponge construction is exploited to enable different modes of operation. An example application outlined in this work is Pseudo Random Number Generation (PRNG). With few adjustments, the KECCAK-CORE was also operated as a post-processing unit for True Random Number Generation (TRNG) that uses the analog Lorenz chaotic circuit as a physical entropy source. The multi-purpose design was implemented in VHDL targeting an IntelFPGA Cyclone-V FPGA. For AES symmetric encryption, a maximum throughput of 31.1Gbps was achieved and a logic usage of 25146LEs (23% of the FPGA) in the case of the pipelined variant of AES-CORE. For the KECCAK-CORE, maximum throughput figures of 5.81, 8.4, and 11Gbps were achieved for the three SHA-3 variants 512, 384, and 256-bit respectively, with an area usage of 8947LEs (8%). The system as a whole occupies an area of 26909LEs (26%). The random sequences generated by the system operating in PRNG and TRNG post- processing modes successfully passed the National Institute of Standards and Technology (NIST) statistical test suite (NIST SP 800-22). The information entropy analysis performed on the post-processed TRNG sequences indicates an average of 0.935.

show abstract

Putting together What Fits together - GrÆStl

Cited by 2 publications

References 17 publications

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3

Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3

Design and Implementation of a flexible Multi-purpose Cryptographic System on low cost FPGA

Contact Info

Product

Resources

About