Pushing the limits of accelerator efficiency while retaining programmability

Nowatzki, Tony; Gangadhan, Vinay; Sankaralingam, Karthikeyan; Wright, Greg

doi:10.1109/hpca.2016.7446051

Cited by 45 publications

(18 citation statements)

References 37 publications

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“…Multicore General Ý Ý ns × × (5) Ý Notes: (1) FPGAs can perform temporal computation, but it is not practical considering the overhead and effectiveness;…”

Section: Out-of-order Processormentioning

confidence: 99%

“…The data come from recent works with technologies below 90nm [21]. (5) Dataflow mechanisms can be supported in software at the task/thread level, e.g., data-triggered multi-threading [32,33]. A thread of computation is initiated when its input data are ready, continuation is ready, or an address is changed.…”

Section: Out-of-order Processormentioning

confidence: 99%

“…(4) We argue that process-in-memory and computation memory should be introduced into CGRA architectures to address the bottleneck of data movement. (5) We argue that programmable memory management is becoming increasingly important as data-intensive applications, e.g., deep learning and big data, gain momentum. A CGRA architecture with flexible memory system could optimize for various access patterns.…”

Section: Prospective Evolutions Of Architecturesmentioning

confidence: 99%

“…The situation becomes even worse for expensive new circuit technology. Overall, both energy efficiency and flexibility have become the main criteria for computing fabrics [5,6].…”

Section: Introductionmentioning

confidence: 99%

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A Survey of Coarse-Grained Reconfigurable Architecture and Design

et al. 2019

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As general-purpose processors have hit the power wall and chip fabrication cost escalates alarmingly, coarsegrained reconfigurable architectures (CGRAs) are attracting increasing interest from both academia and industry, because they offer the performance and energy efficiency of hardware with the flexibility of software. However, CGRAs are not yet mature in terms of programmability, productivity, and adaptability. This article reviews the architecture and design of CGRAs thoroughly for the purpose of exploiting their full potential. First, a novel multidimensional taxonomy is proposed. Second, major challenges and the corresponding state-of-the-art techniques are surveyed and analyzed. Finally, the future development is discussed. CCS Concepts: • Computer systems organization → Reconfigurable computing; • Hardware → Reconfigurable logic and FPGAs; • Theory of computation → Models of computation;

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“…Multicore General Ý Ý ns × × (5) Ý Notes: (1) FPGAs can perform temporal computation, but it is not practical considering the overhead and effectiveness;…”

Section: Out-of-order Processormentioning

confidence: 99%

Section: Out-of-order Processormentioning

confidence: 99%

Section: Prospective Evolutions Of Architecturesmentioning

confidence: 99%

“…The situation becomes even worse for expensive new circuit technology. Overall, both energy efficiency and flexibility have become the main criteria for computing fabrics [5,6].…”

Section: Introductionmentioning

confidence: 99%

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A Survey of Coarse-Grained Reconfigurable Architecture and Design

et al. 2019

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“…Decoupling the utility of specialized hardware from particular workloads has motivated proposals, such as Smart Memories [25], CHARM [7] and LSSD [29], that attempt to partially match the performance and energy efficiency gains of accelerators without giving up programmability. Our approach differs from theirs in that we relinquish programmability not to compromise on performance or efficiency.…”

Section: Additional Related Workmentioning

confidence: 99%

Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration

Cota

Mantovani

Carloni

2016

Proceedings of the 2016 International Conference on Supercomputing

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We present Roca, a technique to reduce the opportunity cost of integrating non-programmable, high-throughput accelerators in general-purpose architectures. Roca exploits the insight that non-programmable accelerators are mostly made of private local memories (PLMs), which are key to the accelerators' performance and energy efficiency. Roca transparently exposes PLMs of otherwise unused accelerators to the cache substrate, thereby allowing the system to extract utility from accelerators even when they cannot directly speed up the system's workload. Roca adds low complexity to existing accelerator designs, requires minimal modifications to the cache substrate, and incurs a modest area overhead that is almost entirely due to additional tag storage. We quantify the utility of Roca by comparing the returns of investing area in either regular last-level cache banks or Roca-enabled accelerators. Through simulation of nonaccelerated multiprogrammed workloads on a 16-core system, we extend a 2MB S-NUCA baseline system to show that a 6MB Roca-enabled last-level cache built upon typical accelerators (i.e. whose area is 66% memory) can, on average, realize 70% of the performance and 68% of the energy efficiency benefits of a same-area 8MB S-NUCA configuration, in addition to the potential orders-of-magnitude efficiency and performance improvements that the added accelerators provide to workloads suitable for acceleration. CCS Concepts •Hardware → Hardware accelerators; Economics of chip design and manufacturing; On-chip resource management; •Computer systems organization → Heterogeneous (hybrid) systems;

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ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Penha

Silva

et al. 2018

Concurrency and Computation

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Summary Dataflow‐based FPGA accelerators have become a promising alternative to deliver energy‐efficient high‐performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high‐level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications. The framework includes an open dataflow operator library, and templates are provided to easily design new operators. The framework also provides a high‐level and an accurate simulation at circuit level with short execution times. Moreover, ADD provides software and hardware APIs to simplify the integration process, extending the benefits of portability from low‐cost FPGA boards to high performance datacenter FPGA platforms. Our framework supports coupling with high‐level programming languages, and it has been validated on two FPGA platforms: the Intel high‐performance CPU‐FPGA heterogeneous computing platform and an educational FPGA kit. We show that our simple approach presents competitive performance, both in time and energy, when compared to multi‐core and GPU accelerators.

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Pushing the limits of accelerator efficiency while retaining programmability

Cited by 45 publications

References 37 publications

A Survey of Coarse-Grained Reconfigurable Architecture and Design

A Survey of Coarse-Grained Reconfigurable Architecture and Design

Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

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