PURR: a primitive for reconfigurable fast reroute

Abstract

Highly dependable communication networks usually rely on some kind of Fast ReRoute (FRR) mechanism which allows to quickly reroute traffic upon failures, entirely in the data plane. This paper studies the design of FRR mechanisms for emerging reconfigurable switches. Our main contribution is an FRR primitive for programmable data planes, PURR, which provides low failover latency and high switch throughput, by avoiding packet recirculation. PURR tolerates multiple concurrent failures and comes with minimal memory requirements, ensuring compact forwarding tables, by unveiling an intriguing connection to classic "string theory" (i.e., stringology), and in particular, the shortest common supersequence problem. PURR is well-suited for high-speed match-action forwarding architectures (e.g., PISA) and supports the implementation of arbitrary network-wide FRR mechanisms. Our simulations and prototype implementation (on an FPGA and Tofino) show that PURR improves TCAM memory occupancy by a factor of 1.5x-10.8x compared to a naïve encoding when implementing state-of-the-art FRR mechanisms. PURR also improves the latency and throughput of datacenter traffic up to a factor of 2.8x-5.5x and 1.2x-2x, respectively, compared to approaches based on recirculating packets.

IntSight

“…As future work, we plan to integrate IntSight with mechanisms to solve the diagnosed SLO violation problems. An attractive future direction is to coordinate quick reactions (that can be activated by the data plane right after an SLO violation is detected, e.g., in line with [8]) with longer-term, strategic decisions, which would work in the control-plane timescale.…”

A Survey of Fast-Recovery Mechanisms in Packet-Switched Networks

“…As first recovery concepts for programmable data planes are emerging, researchers also started investigating general primitives to support an efficient recovery. For example, Chiesa et al [263], [268] suggested an FRR primitive which requires just one lookup in a TCAM, and hence outperforms naive implementations as it avoids packet recirculation. This can improve latency and throughput, and, if deployed as a "primitive", can be used together with many existing FRR mechanisms (which is also demonstrated, e.g., for [269]), allowing them to benefit from avoiding packet recirculation.…”

“…At the same time, new designs will remain constrained by the limitations of programmable devices and by increasing performance requirements. A good example illustrating the trade-off between the resource utilization and performance (in terms of latency and throughput) has been presented in [268].…”

A Survey of Fast Recovery Mechanisms in the Data Plane

“…Most recently, in the context of P4, Chiesa et al [254], [258] suggested an FRR primitive for programmable dataplanes based on P4. Their solution requires just one lookup in a TCAM, and hence outperforms naive implementations as it avoids packet recirculation.…”

“…At the same time, new designs will remain constrained by the limitations of programmable devices and by increasing performance requirements. A good example illustrating the trade-off between the resource utilization and performance (in terms of latency and throughput) has been presented in [258]. Based on the specific subset of parameters which are used by an algorithm to determine the preferred alternative output network interface, the corresponding actions may also be triggered if necessary, both in the context of messages as well as the entire forwarding pipelines maintained by network devices, for example:…”