Pseudorandom Testing

Wagner, K.D.; Chin, Cary K.; McCluskey, E.J.

doi:10.1109/tc.1987.1676905

Cited by 145 publications

(17 citation statements)

References 6 publications

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“…These techniques are generally able to generate test patterns with a high fault coverage and an optimized length, but they suffer from long execution times. Random methods [187] produce test vectors as pseudorandomly generated n-tuples of input values, thus requiring no knowledge of circuit structure. Random methods generate test vectors more quickly than deterministic methods, but need a large number of vectors to ensure a high probability of detecting all faults.…”

Section: Related Work: Testing Techniquesmentioning

confidence: 99%

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

Cassano

2014

2014 International Test Conference

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SommarioI dispositivi FPGA con memoria di configurazione SRAM sono sempre più rilevanti in un grande numero di campi applicativi, dal contesto automobilistico a quello aerospaziale. Questi campi applicativi sono caratterizzati dalla presenza di radiazioni capaci di causare Single Event Upsets (SEUs) in dispositivi digitali. Tali guasti hanno effetti particolarmente dannosi sui sistemi implementati in tecnologia SRAM-based FPGA, in quanto sono in grado non solo di danneggiare temporaneamente il comportamento del sistema, cambiando il contenuto di flip-flop e memorie, ma anche di cambiare permanentemente la funzionalità implementata dal sistema stesso, cambiando il contenuto della memoria di configurazione. Il design di applicazioni safetycritical richiede l'utilizzo, prima possibile durante il flusso di progetto del sistema, di metodologie accurate per la valutazione della sensitività ai SEU del sistema stesso. Inoltre è necessario essere in grado di rilevare l'occorrenza di SEU durante il funzionamento del sistema. A questo scopo è necessario generare test patterns durante il progetto del sistema ed è poi necessario applicare tali test patterns agli input del sistema durante il suo funzionamento.In questa tesi descriviamo il progetto e l'implementazione di strumenti software utili al progettista di applicazioni safety-critical basati su tecnologia SRAM-based FP-GA per la valutazione della sensitività ai SEU del sistema e per la generazione di test pattern utili al rilevamento di SEU nella memoria di configurazione durante la vita del sistema. La caratteristica principale di questi strumenti è l'implementazione di un modello di SEU nei bit di configurazione che controllano le risorse logiche e di routing di un dispositivo FPGA che risulta essere molto più accurato rispetto ai classici modelli stuck-at ed open/short che sono in genere considerati nell'analisi di circuiti digitali. In tal modo gli strumenti proposti risultano essere molto più accurati rispetto a strumenti simili, sia accademici che commerciali, attualmente disponibili per l'analisi dei guasti in dispositivi digitali ma non specificamente sviluppati per dispositivi FPGA.In particolare tre strumenti sono stati progettati ed implementati: (i) ASSESS: Accurate Simulator of SEuS affecting the configuration memory of SRAM-based FPGAs, un simulatore di SEU nella memoria di configurazione di sistemi implementati in tecnologia SRAM-based FPGA, finalizzato a valutare la sensitività del sistema ai SEU prima possibile nel processo di sviluppo del sistema; (ii) UA 2 TPG: Untestability Analyzer and Automatic Test Pattern Generator for SEUs Affecting the Configuration Memory of SRAM-based FPGAs, uno strumento di analisi statica per l'identificazione dei SEU non testabili e per la generazione automatica di test patterns per il rilevamento del 100% dei SEU testabili; e (iii) GABES: Genetic Algorithm Based Environment for SEU Testing in SRAM-FPGAs, un ambiente basato su un algoritmo genetico per la generazione ed ottimizzazione di test patterns per il rilevamento di...

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Section: Related Work: Testing Techniquesmentioning

confidence: 99%

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

Cassano

2014

2014 International Test Conference

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“…Some efforts have analyzed the pseudo-random testing [10][11][12][13]. These efforts used the combinatorial analysis and the differential solution to obtain the detection probability, the input sequence length, the fault coverage, the test confidence, and so on.…”

Section: Introductionmentioning

confidence: 99%

On the testing quality of random and pseudo-random sequences for permanent and intermittent faults

Ding

Wu²

1999

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

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In this paper, the natures of random and pseudo-random input sequences and their influence on permanent and intermittent fault detecting are analyzed. The aliasing fault coverage between the pseudo-random and random sequences is estimated. The activity probability features of the intermittent faults are considered. The selftest circuits of the intermittent faults are illustrated. The experimental results based on real circuits are obtained through simulation. The mathematical analysis and experimental results show that the quality of the pseudorandom testing is better than that of the random testing for the permanent and intermittent faults. The Markov chain models are used in obtaining the input sequence length needed for determining if a circuit fault is intermittent or permanent. I IntroductionThe continually growing complexity of VLSI circuits makes the built-in self-test (BIST) techniques especially attractive [1~3]. In the techniques, two modules: the pseudorandom sequence generator and the output responses compactor, have to be integrated into a VLSI chip. The pseudo-random sequences generated by the generator is applied to the inputs of the circuit under test (CUT) and at the same time, the compactor compresses the CUT responses set into a signature.In most BIST techniques, the linear feedback shift register (LFSR) [4,5] is commonly used in generating the pseudorandom sequences. The responses compaction can be implemented by using the multiple input shift register (MISR) [6], the multiplexed parity trees [7], the transition count [8], the state-difference count [9], and so on. When the pseudo-random input sequences are applied to the CUT, the compactor compresses the CUT output responses simultaneously. After finishing the testing, the compressed signature will be compared with the expectant reference value produced by a corresponding fault-free circuit. If the two values are the same, the CUT testing will be considered pass; otherwise, the CUT will be considered faulty.However, the pseudo-random sequences generated by the LFSR used in the BIST techniques are not completely random. Therefore, the natures of the pseudo-random input sequences and the effectiveness of the compact approaches need to be analyzed.Some efforts have analyzed the pseudo-random testing [10][11][12][13]. These efforts used the combinatorial analysis and the differential solution to obtain the detection probability, the input sequence length, the fault coverage, the test confidence, and so on. The results of these efforts showed that the random test model is not a better approximation to the pseudo-random testing. However, the relationship among the input sequence length, the testability, and the fault coverage was not described in these efforts. Especially, the aliasing fault coverage between the random and pseudo-random sequences was not discussed.In this paper, we will analyze the relationship among the input sequence length, the testability, and the fault coverage for the random and pseudo-random testing, and estimate ...

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“…Analytical and approximate testability analysis of circuits for static stuck-at type fault models have been widely discussed [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21]. These analytical and approximate methods estimate probabilities and detectabilities for non-redundant combinational circuits as well as general combinational circuits.…”

Section: Introductionmentioning

confidence: 99%

Statistical estimation of delay fault detectabilities and fault grading

1996

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In this paper we present a technique to statistically estimate transition delay and path delay fault coverage. The basic method is an extension of STAFAN to include delay faults. By partitioning a combinational circuit into non-overlapping fanout free logic cones, we accurately calculate the transition sensitization controllabilities of 0 ~ 1 and 1 -~ 0 transitions of the lines within a fanout free logic cone to the output of the fanout free logic cone for each fanout free logic cone. A strategy to calculate the transition observabilities of fanout stems is proposed.The detectability of a path delay fault is evaluated as the product of the observabilities of the input line to its head gate within each fanout free logic cone on the path multiplied by the transition controllability of the path. When compared with the fault simulations, the estimations of transition delay fault coverage are within 2.3%. Also, the technique gives reasonably good path delay fault coverage estimation for large fault set of the ISCAS 85 benchmark circuits.

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Pseudorandom Testing

Cited by 145 publications

References 6 publications

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

On the testing quality of random and pseudo-random sequences for permanent and intermittent faults

Statistical estimation of delay fault detectabilities and fault grading

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