Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits

Abstract

This work proposes a pseudo-differential timedomain integrator using half-delay time-domain registers and adders relying on charge-based time-domain circuits. It is implemented using a 65-nm CMOS Technology and performs first order integration of time-domain information within the range of [4 ns, -4 ns] across temperature -40 o C to 80 o C. It consumes 740 µW with a supply voltage of 1.2 V at a 100 MHz clock frequency. A delay-locked-loop (DLL) based foreground calibration is used to compensate for process and temperature variations. Index Terms-Time-domain amplifier, time-domain adder, time integrator, half-delay, delay-locked-loop (DLL) clock cycles similar to first order integration in discrete-time voltage-domain signal processing.

A 3rd-Order FIR Filter Implementation Based on Time-Mode Signal Processing

“…The FIR/IIR counterpart implementations in time-mode require the basic operators to work in time domain which means that z −1 , adders [4,7,8] and multipliers [9,10] must be able to handle time-mode quantities [11]. These systems are categorized as discretetime/continuous signal processing (DT-CSP) systems [12].…”