Pruned Bit-Reversal Permutations: Mathematical Characterization, Fast Algorithms and Architectures

Abstract

A mathematical characterization of serially-pruned permutations (SPPs) employed in variable-length permuters and their associated fast pruning algorithms and architectures are proposed. Permuters are used in many signal processing systems for shuffling data and in communication systems as an adjunct to coding for error correction. Typically only a small set of discrete permuter lengths are supported. Serial pruning is a simple technique to alter the length of a permutation to support a wider range of lengths, but results in a serial processing bottleneck. In this paper, parallelizing SPPs is formulated in terms of recursively computing sums involving integer floor and related functions using integer operations, in a fashion analogous to evaluating Dedekind sums. A mathematical treatment for bit-reversal permutations (BRPs) is presented, and closed-form expressions for BRP statistics including descents/ascents, major index, excedances/descedances, inversions, and serial correlations are derived. It is shown that BRP sequences have weak correlation properties. Moreover, a new statistic called permutation inliers that characterizes the pruning gap of pruned interleavers is proposed. Using this statistic, a recursive algorithm that computes the minimum inliers count of a pruned BR interleaver (PBRI) in logarithmic time complexity is presented. This algorithm enables parallelizing a serial PBRI algorithm by any desired parallelism factor by computing the pruning gap in lookahead rather than a serial fashion, resulting in significant reduction in interleaving latency and memory overhead. Extensions to 2-D block and stream interleavers, as well as applications to pruned fast Fourier transforms and LTE turbo interleavers, are also presented. Moreover, hardware-efficient architectures for the proposed algorithms are developed. Simulation results of interleavers employed in modern communication standards demonstrate 3 to 4 orders of magnitude improvement in interleaving time compared to existing approaches.

Impact of Interleaver Pruning on Properties of Underlying Permutations

“…There are several drawbacks to such an approach, one is in terms of implementation complexity that can be significantly higher than more hardware oriented approaches, the other is speed whereby a hardware based solution can generally run much faster than a RAM based approach and finally the fact that one must design the system a-priori and by its very nature the design is inflexible (i.e., one could not change the interleaving block length at will). The idea of using a good mother interleaver and constructing a variable length interleaver out of it via a clever strategy is clearly appealing and that is what this paper and the approach presented in [8], [4], [5], [6] is all about. In coding, a good low rate code is punctured to get higher rate codes.…”

“…The principle goal of pruning is that of construction of variable length and hence delay interleavers with application to iterative soft information processing and concatenated codes. In a series of recent papers [4], [5], [6] M. M. Mansour has developed a systematic and efficient technique for determination of permutation inliers that can be used for construction of variable length interleavers. Our approach is fundamentally different.…”

CRCSI: A Generic Block Interleaver for the Next Generation Terrestrial Broadcast Systems

“…Note that k 1 = 1, k 2 = N and k 1 = M, k 2 = 1 denote the row-wise and column-wise reading, respectively. Here, π 1 and π 2 follow the mapping rules defined in (1).…”

“…In order to improve the reliability of wireless transmission, it is necessary to introduce interleaving technologies into the system, where the transmitted bit or symbol sequence is reordered according to a specific interleaving rule to repair the channel damage caused by burst errors [1].…”