PRTSM: Hardware Data Arrangement Mechanisms for Convolutional Layer Computation on the Systolic Array

Abstract

The systolic array is an array of processing units which share the inner data flow. Since the 2D systolic array fits the operation of multiplication and accumulation (MAC) naturally, there are many groups which use the systolic array to accelerate the computation of DNN (Deep Neural Network). However, the performance of the systolic array is limited by the data bandwidth. Some groups solve this problem with the method of loop tiling and care little about the pixel reuse potential of the convolutional layer. In this paper, we propose a novel method of PRTSM (Pixels Reuse with Time and Spatial Multiplexing) which reuses the pixels of the input feature map with time and spatial multiplexing. With it, we can significantly reduce the pressure of bandwidth and save the time of data preparing for convolutional layers on the systolic array. We propose three algorithms for this method and implement the corresponding hardware mechanisms on Xilinx FPGA XCVU440. Experiments show that our hardware mechanisms can reduce at least 72.03% of the offchip traffic. The mechanisms proposed by this paper can reach a peak performance of 64.034 GOPS with a frequency of 167M Hz.

Design and Implementation of Handwritten Digit Recognition Accelerator Based on Systolic Array

“…As shown in Figure 4, by dividing the array into multiple small arrays into multiple Brams, multiple data can be accessed in one cycle. A [12] Local_a0 [3] Local_a1 [3] Local_a2 [3] Local_a3 [3]…”

“…In [12], the authors proposed a convolutional computation unit based on a systolic array. However, the implemented systolic array is relatively small, and the input feature map is also too small, only 7*7*3, which results in the underutilization of the board's resources.…”