Design and Implementation of Handwritten Digit Recognition Accelerator Based on Systolic Array

Abstract

Due to the rapid development in artificial intelligence, the classic Von Neumann architecture is no longer able to meet the demands of high-computing, high-storage, and high-bandwidth artificial intelligence applications. To address this issue, this paper proposes a handwritten digit recognition accelerator based on a systolic array. First, a 5 convolutional layer handwritten digit recognition network is built. Besides, The FPGA-based convolution accelerator employs im2col technology to convert convolution calculations into matrix multiplications and uses a systolic array to efficiently perform these multiplications. Furthermore, the four convolution processes are pipelined to improve the throughput. Finally, a handwritten digit recognition system is implemented on the PYNQ-Z2. Compared with the software implementation on Arm, the speedup of the accelerator is 598x, the delay is 1.24 s, and the power consumption is 2.51 w.