Provably secure camouflaging strategy for IC protection

Li, Meng; Shamsi, Kaveh; Meade, Travis; Zhao, Zheng; Yu, Bei; Jin, Yier; Pan, David Z.

doi:10.1145/2966986.2967065

Cited by 92 publications

(65 citation statements)

References 14 publications

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“…The resulting camouflaging limit (right) is the ratio of cells that can be camouflaged over total cell instances, the latter as obtained by regular synthesis using the full library (left). Cells described as relevant for XOR-type camouflaging in [17]: BUF, INV, AND2, NAND2, OR2, NOR2, AND3, NAND3; cells described as relevant for STF-type camouflaging in [17]: BUF, INV, AND2, NAND2, OR2, AND3; cells assumed relevant for XOR-NAND-NOR camouflaging [7]: XOR2, NAND2, NOR2; cells assumed relevant for threshold-dependent camouflaging [11]: AND2, NAND2, NOR2, OR2, XOR2, XNOR2. remain largely as is, and additional steps are only required for preparation, shipping, and finalization of FEOL wafers.…”

Section: A Split Manufacturingmentioning

confidence: 99%

“…Several studies on provably secure camouflaging (and logic locking), e.g., see [17]- [19], [44], seek to mitigate SAT-based attacks by inserting dedicated structures which necessitate considering an exponential number of I/O patterns. However, the output signals related to such structures have been identified successfully, e.g., by signal-probability-or sensitization-driven algorithms [23], [45], [46].…”

Section: Ieee Transactions On Computer-aided Design Of Integrated Cirmentioning

confidence: 99%

“…Bench-XOR-type [17] STF-type [17] Threshold [ We consider selected ISCAS-85 and ITC-99 benchmarks, as done in the listed prior art.…”

Section: Table VII Area (A) Power (P) and Delay (D) For Full-chip Cmentioning

confidence: 99%

“…Comparison with provably secure camouflaging: Recall that schemes like [17]- [19] rely on additional circuitry to protect individual, selected gates, wires, or outputs. Such circuitry can incur a high cost, especially for area and power.…”

Section: Table VII Area (A) Power (P) and Delay (D) For Full-chip Cmentioning

confidence: 99%

“…Still, it is not straightforward to prove beforehand to what extent large-scale camouflaging will render a layout resilient without actually leveraging a SAT solver's capabilities for de-camouflaging attacks. Li et al [17] have shown that decamouflaging efforts scale on average with (i) the solution space C concerning all possible functionalities of the whole design and (ii) the Hamming distances among those different functionalities. A further theoretical evaluation of large-scale camouflaging is difficult since C depends on (i) the number and composition of possible functionalities supported by the camouflaging primitives, (ii) the number of camouflaged gates, (iii) the selection of camouflaged gates, and (iv) the interconnectivity of the design, all at the same time.…”

Section: Security Evaluation: Malicious End-users Sat-based Attacksmentioning

confidence: 99%

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Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

Patnaik¹,

Ashraf²,

Knechtel³

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Layout camouflaging can protect the intellectual property of modern circuits. Most prior art, however, incurs excessive layout overheads and necessitates customization of active-device manufacturing processes, i.e., the front-end-of-line (FEOL). As a result, camouflaging has typically been applied selectively, which can ultimately undermine its resilience. Here, we propose a low-cost and generic scheme-full-chip camouflaging can be finally realized without reservations. Our scheme is based on obfuscating the interconnects, i.e., the back-end-ofline (BEOL), through design-time handling for real and dummy wires and vias. To that end, we implement custom, BEOL-centric obfuscation cells, and develop a CAD flow using industrial tools. Our scheme can be applied to any design and technology node without FEOL-level modifications. Considering its BEOL-centric nature, we advocate applying our scheme in conjunction with split manufacturing, to furthermore protect against untrusted fabs. We evaluate our scheme for various designs at the physical, DRC-clean layout level. Our scheme incurs a significantly lower cost than most of the prior art. Notably, for fully camouflaged layouts, we observe average power, performance, and area overheads of 24.96%, 19.06%, and 32.55%, respectively. We conduct a thorough security study addressing the threats (attacks) related to untrustworthy FEOL fabs (proximity attacks) and malicious end-users (SAT-based attacks). An empirical key finding is that only large-scale camouflaging schemes like ours are practically secure against powerful SAT-based attacks. Another key finding is that our scheme hinders both placement-and routing-centric proximity attacks; correct connections are reduced by 7.47X, and complexity is increased by 24.15X, respectively, for such attacks.

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